Inventor

GRADSTEIN AMIT

IL132 patents

⚠️ This page may combine multiple inventors who share the name “GRADSTEIN AMIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRADSTEIN AMIT

INTEL CORP

Systems and methods to load a tile register pair

Systems and methods to zero a tile register pair

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing instructions to transpose rectangular tiles

Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions

Matrix transpose and multiply

Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems, methods, and apparatuses for matrix operations

Systems and methods to store a tile register pair to memory

Systems and methods for computing dot products of nibbles in two tile operands

Systems, methods, and apparatuses for dot product operations

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods to load a tile register pair

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for performing instructions to convert to 16-bit floating-point format

Using Fuzzy-Jbit location of floating-point multiply-accumulate results

Systems and methods to zero a tile register pair

Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator

Systems and methods to perform floating-point addition with selected rounding

Systems, apparatuses, and methods for fused multiply add

Vector mask driven clock gating for power efficiency of a processor

Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions

Apparatuses, methods, and systems for instructions of a matrix operations accelerator

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Systems and methods for performing 16-bit floating-point vector dot product instructions

Systems and methods for performing 16-bit floating-point vector dot product instructions

Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset

Apparatus and method of improved packed integer permute instruction

Linear memory address transformation and management

Floating point scaling processors, methods, systems, and instructions

Floating point scaling processors, methods, systems, and instructions

Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset

Methods, apparatus, instructions and logic to provide vector packed tuple cross-comparison functionality

Floating point round-off amount determination processors, methods, systems, and instructions

Apparatuses, methods, and systems for hashing instructions

Apparatuses, methods, and systems for hashing instructions

GUERON SHAY

Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation

Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation

OULD-AHMED-VALL ELMOUSTAPHA

Packed rotate processors, methods, systems, and instructions

Systems, apparatuses, and methods for performing a double blocked sum of absolute differences

PINEIRO JOSE-ALEJANDRO

Math circuit for estimating a transcendental function

HAGOG MOSTAFA

Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction

GRADSTEIN AMIT

Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions

RUBANOVICH SIMON

Fused multiply add operations using bit masks

ANDERSON CHRISTINA S

Floating point scaling processors, methods, systems, and instructions

OULD AHMED VALL ELMOUSTAPHA

Packed data rearrangement control indexes generation processors, methods, systems and instructions