Inventor

YOO CHAN H

US64 patents

⚠️ This page may combine multiple inventors who share the name “YOO CHAN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOO CHAN H

MICRON TECHNOLOGY INC

Memory device interface and method

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Dual sided fan-out package having low warpage across all temperatures

Thrumold post package with reverse build up hybrid additive structure

Semiconductor devices with flexible reinforcement structure

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

Tubular heat spreaders for memory modules and memory modules incorporating the same

Semiconductor assemblies including thermal circuits and methods of manufacturing the same

Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer

Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer

Interposers for microelectronic devices

Interposers for microelectronic devices

Semiconductor device having laterally offset stacked semiconductor dies

Semiconductor device modules including a die electrically connected to posts and related methods

Device module having a plurality of dies electrically connected by posts

Methods of making semiconductor device modules with increased yield

Semiconductor devices with flexible reinforcement structure

Stacked interposer structures

Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer

Low cost three-dimensional stacking semiconductor assemblies

Semiconductor devices with flexible reinforcement structure

Semiconductor assemblies including thermal circuits and methods of manufacturing the same

Dual sided fan-out package having low warpage across all temperatures

Stress tuned stiffeners for micro electronics package warpage control

Interposer, microelectronic device assembly including same and methods of fabrication

Low cost three-dimensional stacking semiconductor assemblies

Stacked interposer structures, microelectronic device assemblies including same, and methods of fabrication, and related electronic systems

Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer

Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same

Dual sided fan-out package having low warpage across all temperatures

Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to system board

Memory device interface and method

Substrates for semiconductor device assemblies and systems with improved thermal performance and methods for making the same

Interposers for microelectronic devices

Semiconductor interconnect structures with conductive elements, and associated systems and methods

Methods of forming microelectronic device assemblies and packages

Semiconductor device having laterally offset stacked semiconductor dies

Semiconductor interconnect structures with conductive elements, and associated systems and methods

Memory modules and memory packages including graphene layers for thermal management

LODESTAR LICENSING GROUP LLC

Memory device interface and method

Memory device interface and method

Methods for memory power management and memory devices and systems employing the same

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

KOREA ELECTRONICS TELECOMM

Method for controlling overload of main processor of distributed switching system with hierarchy structure

Method for controlling overload in centralized and distributed operating hybrid switching system

Method for controlling overload of distributed processors of full electronic switching system

INTEL CORP

Vertical taper waveguide