Inventor
IMTHURN GEORGE
US27 patents
⚠️ This page may combine multiple inventors who share the name “IMTHURN GEORGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PSEMI CORP
11 patentsUS10680600B2Jun 9, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP21 citations98
US10622990B2Apr 14, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP20 citations98
US10153763B2Dec 11, 2018
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP24 citations98
US10790815B2Sep 29, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP11 citations94
US10797690B2Oct 6, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP10 citations93
US10797691B1Oct 6, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP10 citations93
US10790814B2Sep 29, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP10 citations93
US10784855B2Sep 22, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP10 citations93
US10797172B2Oct 6, 2020
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
PSEMI CORP10 citations92
US11967948B2Apr 23, 2024
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP0 citations73
US11362652B2Jun 14, 2022
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PSEMI CORP0 citations73
SILANNA ASIA PTE LTD
9 patentsUS10192983B2Jan 29, 2019
LDMOS with adaptively biased gate-shield
SILANNA ASIA PTE LTD6 citations82
US9559199B2Jan 31, 2017
LDMOS with adaptively biased gate-shield
SILANNA ASIA PTE LTD8 citations82
US11742396B2Aug 29, 2023
Threshold voltage adjustment using adaptively biased shield plate
SILANNA ASIA PTE LTD2 citations71
US11171215B2Nov 9, 2021
Threshold voltage adjustment using adaptively biased shield plate
SILANNA ASIA PTE LTD4 citations71
US10636905B2Apr 28, 2020
LDMOS with adaptively biased gate-shield
SILANNA ASIA PTE LTD2 citations71
US11011615B2May 18, 2021
Transistor with contacted deep well region
SILANNA ASIA PTE LTD1 citations62
US12100740B2Sep 24, 2024
Threshold voltage adjustment using adaptively biased shield plate
SILANNA ASIA PTE LTD0 citations61
US10381457B2Aug 13, 2019
Transistor with contacted deep well region
SILANNA ASIA PTE LTD0 citations52
US9780189B2Oct 3, 2017
Transistor with contacted deep well region
SILANNA ASIA PTE LTD0 citations52
PEREGRINE SEMICONDUCTOR CORP
5 patentsUS9780775B2Oct 3, 2017
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PEREGRINE SEMICONDUCTOR CORP32 citations98
US9130564B2Sep 8, 2015
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
PEREGRINE SEMICONDUCTOR CORP35 citations98
US7524710B2Apr 28, 2009
Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
PEREGRINE SEMICONDUCTOR CORP8 citations80
US7411250B2Aug 12, 2008
Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
PEREGRINE SEMICONDUCTOR CORP0 citations48
US9390942B2Jul 12, 2016
Method, system, and apparatus for preparing substrates and bonding semiconductor layers to substrates
PEREGRINE SEMICONDUCTOR CORP0 citations35