Inventor
CANO FRANCISCO A
US13 patents
⚠️ This page may combine multiple inventors who share the name “CANO FRANCISCO A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TEXAS INSTRUMENTS INC
12 patentsUS6308307B1Oct 23, 2001
Method for power routing and distribution in an integrated circuit with multiple interconnect layers
TEXAS INSTRUMENTS INC70 citations96
US6363516B1Mar 26, 2002
Method for hierarchical parasitic extraction of a CMOS design
TEXAS INSTRUMENTS INC84 citations94
US6038383AMar 14, 2000
Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability
TEXAS INSTRUMENTS INC137 citations93
US6581201B2Jun 17, 2003
Method for power routing and distribution in an integrated circuit with multiple interconnect layers
TEXAS INSTRUMENTS INC44 citations92
US6253359B1Jun 26, 2001
Method for analyzing circuit delays caused by capacitive coupling in digital circuits
TEXAS INSTRUMENTS INC53 citations92
US5745421AApr 28, 1998
Method and apparatus for self-timed precharge of bit lines in a memory
TEXAS INSTRUMENTS INC35 citations90
US6381704B1Apr 30, 2002
Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor
TEXAS INSTRUMENTS INC28 citations88
US11831309B2Nov 28, 2023
Stress reduction on stacked transistor circuits
TEXAS INSTRUMENTS INC3 citations71
US11626875B2Apr 11, 2023
Stress reduction on stacked transistor circuits
TEXAS INSTRUMENTS INC3 citations71
US5835421ANov 10, 1998
Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory
TEXAS INSTRUMENTS INC12 citations71
US12476636B2Nov 18, 2025
Stress reduction on stacked transistor circuits
TEXAS INSTRUMENTS INC0 citations61
US12212317B2Jan 28, 2025
Stress reduction on stacked transistor circuits
TEXAS INSTRUMENTS INC0 citations61