Inventor

KHOUEIR ANTOINE

US67 patents

⚠️ This page may combine multiple inventors who share the name “KHOUEIR ANTOINE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHOUEIR ANTOINE

SEAGATE TECHNOLOGY LLC

Open block refresh management

Open block stability scanning

Non-volatile write buffer data retention pending scheduled verification

Memory with separate read and write paths

Background reads to condition programmed semiconductor memory cells

Magnetic stack design

Open block stability scanning

Monitoring a memory for retirement

Wear-based access optimization

Open block management

Post-program conditioning of stacked memory cells prior to an initial read operation

Memory device having memory cells connected in parallel to common source and drain and method of fabrication

Three dimensional floating gate NAND memory

ECC management for variable resistance memory cells

Optimization of variable resistance memory cells

Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory

NAND based resistive sense memory cell architecture

NAND based resistive sense memory cell architecture

End of life extension of solid state memory

Active protection device for resistive random access memory (RRAM) formation

Fast soft data by detecting leakage current and sensing time

Method of fabricating a magnetic stack design with decreased substrate stress

Partial reprogramming of solid-state non-volatile memory cells

Data update management in a cloud computing environment

Fast error recovery with error correction code (ECC) syndrome weight assist

Selecting between non-volatile memory units having different minimum addressable data unit sizes

Applying a bias signal to memory cells to reverse a resistance shift of the memory cells

Data protection for unexpected power loss

Non-volatile, solid-state memory configured to perform logical combination of two or more blocks sharing series-connected bit lines

Programming a memory cell using a dual polarity charge pump

Background reads to condition programmed semiconductor memory cells

Mitigation of solid state memory read failures with a testing procedure

Master set of read voltages for a non-volatile memory (NVM) to mitigate cross-temperature effects

Adjusting code rates to mitigate cross-temperature effects in a non-volatile memory (NVM)

Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory

Temperature based logic profile for variable resistance memory cells

Memory with separate read and write paths

Detection and mitigation for solid-state storage device read failures due to weak erase

Extending the life of a solid state drive by using MLC flash blocks in SLC mode

Data refresh in flash memory

Three dimensional resistive memory

XI HAIWEN

Non-volatile memory cell with lateral pinning

Memory with separate read and write paths

Magnetic stack design

Memory with separate read and write paths

DIMITROV DIMITAR V

Memory cell with stress-induced anisotropy

AHN YONGCHUL

nvSRAM having variable magnetic resistors

LEE HYUNG-KYU

Patterning embedded control lines for vertically stacked semiconductor elements

KIM YOUNGPIL

Soft erasure of memory cells

KHOUEIR ANTOINE

Semiconductor topography and method for reducing gate induced drain leakage (GIDL) in MOS transistors