P

Inventor

VASUDEVAN ANIL

US114 patents
⚠️ This page may combine multiple inventors who share the name “VASUDEVAN ANIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

30 patents
US6922722B1Jul 26, 2005

Method and apparatus for dynamic network configuration of an alert-based client

INTEL CORP77 citations97
US7117280B2Oct 3, 2006

Network based intra-system communications architecture

INTEL CORP56 citations96
US7949794B2May 24, 2011

PCI express enhancements and extensions

INTEL CORP41 citations95
US7318089B1Jan 8, 2008

Method and apparatus for performing network-based control functions on an alert-enabled managed client

INTEL CORP85 citations94
US7206833B1Apr 17, 2007

Platform independent alert detection and management

INTEL CORP33 citations93
US7930566B2Apr 19, 2011

PCI express enhancements and extensions

INTEL CORP13 citations92
US7899943B2Mar 1, 2011

PCI express enhancements and extensions

INTEL CORP16 citations92
US7788391B2Aug 31, 2010

Using a threshold value to control mid-interrupt polling

INTEL CORP11 citations92
US6671722B1Dec 30, 2003

Stack-less, CPU-less creation of valid SNMP-trap packets

INTEL CORP33 citations92
US6629248B1Sep 30, 2003

Apparatus and method for maintaining a security association for manageability across power failures

INTEL CORP43 citations92
US7783769B2Aug 24, 2010

Accelerated TCP (Transport Control Protocol) stack processing

INTEL CORP13 citations91
US11816036B2Nov 14, 2023

Method and system for performing data movement operations with read snapshot and in place write update

INTEL CORP11 citations84
US9535838B2Jan 3, 2017

Atomic operations in PCI express

INTEL CORP2 citations84
US9098415B2Aug 4, 2015

PCI express transaction descriptor

INTEL CORP4 citations84
US9032103B2May 12, 2015

Transaction re-ordering

INTEL CORP5 citations84
US9026682B2May 5, 2015

Prefectching in PCI express

INTEL CORP5 citations84
US7987307B2Jul 26, 2011

Interrupt coalescing control scheme

INTEL CORP12 citations84
US7480747B2Jan 20, 2009

Method and apparatus to reduce latency and improve throughput of input/output data in a processor

INTEL CORP9 citations84
US6915431B1Jul 5, 2005

System and method for providing security mechanisms for securing network communication

INTEL CORP19 citations84
US10606755B2Mar 31, 2020

Method and system for performing data movement operations with read snapshot and in place write update

INTEL CORP5 citations82
US10547559B2Jan 28, 2020

Application-level network queueing

INTEL CORP6 citations79
US7525967B2Apr 28, 2009

Techniques to control access to logic

INTEL CORP7 citations74
US10503684B2Dec 10, 2019

Multiple uplink port devices

INTEL CORP4 citations73
US10142231B2Nov 27, 2018

Technologies for network I/O access

INTEL CORP6 citations73
US9979640B2May 22, 2018

Reorder resilient transport

INTEL CORP2 citations73
US11843550B2Dec 12, 2023

Packet processing with reduced latency

INTEL CORP1 citations72
US11178076B2Nov 16, 2021

Packet processing with reduced latency

INTEL CORP1 citations72
US10476818B2Nov 12, 2019

Packet processing with reduced latency

INTEL CORP1 citations72
US9608842B2Mar 28, 2017

Providing, at least in part, at least one indication that at least one portion of data is available for processing

INTEL CORP2 citations72
US11327894B2May 10, 2022

Method and system for performing data movement operations with read snapshot and in place write update

INTEL CORP2 citations71

AJANOVIC JASMIN

9 patents

ABBOTT LAB

5 patents

ABBVIE INC

2 patents

CORNETT LINDEN

2 patents

AKRITOPOULOU-ZANZE IRINI

1 patent

VASUDEVAN ANIL

1 patent

Showing the top 50 of 114 patents by PatentIndex Score.