Inventor

HERDRICH ANDREW J

US68 patents

⚠️ This page may combine multiple inventors who share the name “HERDRICH ANDREW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HERDRICH ANDREW J

INTEL CORP

Function as a service (FaaS) system enhancements

Technologies for allocating resources within a self-managed node

Parallel processing of service functions in service function chains

Cache-aware adaptive thread scheduling and migration

Out-of-band platform tuning and configuration

Method and system for performing data movement operations with read snapshot and in place write update

Technologies for managing sensor and telemetry data on an edge networking platform

Cache monitoring

Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers

Techniques to dynamically allocate resources of configurable computing resources

Method and system for performing data movement operations with read snapshot and in place write update

Multi-core communication acceleration using hardware queue device

Apparatus and method for a resource allocation control framework using performance markers

Techniques to migrate a virtual machine using disaggregated computing resources

Arbitration across shared memory pools of disaggregated memory devices

Cache allocation with code and data prioritization

Cache allocation with code and data prioritization

Methods and apparatus to manage quality of service with respect to service level agreements in a computing device

Technologies for autonomous edge compute instance optimization and auto-healing using local hardware platform QoS services

Mobile edge-cloud security infrastructure

Power efficient processor architecture

Method and apparatus for accelerating VM-to-VM network traffic using CPU cache

Out-of-band platform tuning and configuration

Method for booting a heterogeneous system and presenting a symmetric core view

Apparatus and method for heterogeneous processors mapping to virtual cores

Hetergeneous processor apparatus and method

Managing data center resources to achieve a quality of service

Method and system for performing data movement operations with read snapshot and in place write update

Techniques to manage cache resource allocations for a processor cache

Managing data center resources to achieve a quality of service

Quality of service (QoS) management in edge computing environments

Real-time local and global datacenter network optimizations based on platform telemetry data

Efficient resource allocation for service level compliance

Infrastructure processing unit

Aperture access processors, methods, systems, and instructions

Aperture access processors, methods, systems, and instructions

Fabric support for quality of service

Processor and method implementing a cacheline demote machine instruction

Cache monitoring

Processors and methods for managing cache tiering with gather-scatter vector semantics

Power efficient processor architecture

Power efficient processor architecture

Hetergeneous processor apparatus and method

Dynamic quality of service in edge cloud architectures

Technologies for autonomous edge compute instance optimization and auto-healing using local hardware platform QoS services

Dynamic quality of service in edge cloud architectures

Controller for locking of selected cache regions

HERDRICH ANDREW J

End-to-end datacenter performance control

Power efficient processor architecture

MOSES JAIDEEP

Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing