Inventor
QIAN ZHIGUO
US75 patents
⚠️ This page may combine multiple inventors who share the name “QIAN ZHIGUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
45 patentsUS9275971B2Mar 1, 2016
Bridge interconnect with air gap in package assembly
INTEL CORP33 citations98
US9515017B2Dec 6, 2016
Ground via clustering for crosstalk mitigation
INTEL CORP12 citations93
US11621227B2Apr 4, 2023
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP6 citations86
US11222848B2Jan 11, 2022
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP6 citations86
US10950550B2Mar 16, 2021
Semiconductor package with through bridge die connections
INTEL CORP10 citations86
US11837549B2Dec 5, 2023
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP3 citations84
US10658279B2May 19, 2020
High density package interconnects
INTEL CORP6 citations84
US9806011B2Oct 31, 2017
Non-uniform substrate stackup
INTEL CORP7 citations84
US9542522B2Jan 10, 2017
Interconnect routing configurations and associated techniques
INTEL CORP6 citations84
US9230900B1Jan 5, 2016
Ground via clustering for crosstalk mitigation
INTEL CORP9 citations84
US10692847B2Jun 23, 2020
Inorganic interposer for multi-chip packaging
INTEL CORP7 citations80
US12107060B2Oct 1, 2024
Microelectronic assemblies with inductors in direct bonding regions
INTEL CORP5 citations75
US12062616B2Aug 13, 2024
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP2 citations73
US11984439B2May 14, 2024
Microelectronic assemblies
INTEL CORP2 citations73
US11901280B2Feb 13, 2024
Ground via clustering for crosstalk mitigation
INTEL CORP2 citations73
US11817391B2Nov 14, 2023
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP3 citations73
US11450560B2Sep 20, 2022
Microelectronic assemblies having magnetic core inductors
INTEL CORP3 citations73
US11450613B2Sep 20, 2022
Integrated circuit package with test circuitry for testing a channel between dies
INTEL CORP4 citations73
US10748842B2Aug 18, 2020
Package substrates with magnetic build-up layers
INTEL CORP1 citations73
US10204851B2Feb 12, 2019
High density package interconnects
INTEL CORP1 citations73
US10056528B1Aug 21, 2018
Interposer structures, semiconductor assembly and methods for forming interposer structures
INTEL CORP4 citations73
US10026682B2Jul 17, 2018
Ground via clustering for crosstalk mitigation
INTEL CORP2 citations73
US9922916B2Mar 20, 2018
High density package interconnects
INTEL CORP3 citations73
US10845552B2Nov 24, 2020
Coreless package architecture for multi-chip opto-electronics
INTEL CORP4 citations72
US10784204B2Sep 22, 2020
Rlink—die to die channel interconnect configurations to improve signaling
INTEL CORP3 citations72
US10103054B2Oct 16, 2018
Coupled vias for channel cross-talk reduction
INTEL CORP4 citations72
US11276635B2Mar 15, 2022
Horizontal pitch translation using embedded bridge dies
INTEL CORP2 citations71
US10840196B1Nov 17, 2020
Trace modulations in connectors for integrated-circuit packages
INTEL CORP4 citations70
US11031341B2Jun 8, 2021
Side mounted interconnect bridges
INTEL CORP2 citations66
US12482733B2Nov 25, 2025
Ground via clustering for crosstalk mitigation
INTEL CORP0 citations63
US11923308B2Mar 5, 2024
Die interconnect structures having bump field and ground plane
INTEL CORP0 citations63
US11742275B2Aug 29, 2023
Ground via clustering for crosstalk mitigation
INTEL CORP0 citations63
US11682613B2Jun 20, 2023
Package substrates with magnetic build-up layers
INTEL CORP0 citations63
US11387188B2Jul 12, 2022
High density interconnect structures configured for manufacturing and performance
INTEL CORP0 citations63
US11244890B2Feb 8, 2022
Ground via clustering for crosstalk mitigation
INTEL CORP0 citations63
US11222847B2Jan 11, 2022
Enabling long interconnect bridges
INTEL CORP0 citations63
US11081434B2Aug 3, 2021
Package substrates with magnetic build-up layers
INTEL CORP0 citations63
US10892225B2Jan 12, 2021
Die interconnect structures and methods
INTEL CORP1 citations63
US10283453B2May 7, 2019
Interconnect routing configurations and associated techniques
INTEL CORP1 citations63
US9589866B2Mar 7, 2017
Bridge interconnect with air gap in package assembly
INTEL CORP1 citations63
US9232639B2Jan 5, 2016
Non-uniform substrate stackup
INTEL CORP2 citations63
US12538823B2Jan 27, 2026
Power delivery for embedded bridge die utilizing trench structures
INTEL CORP0 citations62
US12347788B2Jul 1, 2025
Glass substrates having signal shielding for use with semiconductor packages and related methods
INTEL CORP0 citations62
US11887932B2Jan 30, 2024
Dielectric-filled trench isolation of vias
INTEL CORP0 citations62
US11545416B2Jan 3, 2023
Minimization of insertion loss variation in through-silicon vias (TSVs)
INTEL CORP0 citations62
QIAN ZHIGUO
2 patentsCHIU CHIA-PIN
1 patentGANESAN SANKA
1 patentSONG HONGJIANG
1 patentShowing the top 50 of 75 patents by PatentIndex Score.