Inventor

Sporer Ryan

US16 patents

⚠️ This page may combine multiple inventors who share the name “Sporer Ryan”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLOBALFOUNDRIES INC

8 patents

US10043893B1Aug 7, 2018

Post gate silicon germanium channel condensation and method for producing the same

GLOBALFOUNDRIES INC5 citations82

US9806170B1Oct 31, 2017

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

GLOBALFOUNDRIES INC12 citations80

US9875936B1Jan 23, 2018

Spacer defined fin growth and differential fin width

GLOBALFOUNDRIES INC2 citations71

US10522655B2Dec 31, 2019

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

GLOBALFOUNDRIES INC3 citations69

US10217660B2Feb 26, 2019

Technique for patterning active regions of transistor elements in a late manufacturing stage

GLOBALFOUNDRIES INC2 citations68

US10326007B2Jun 18, 2019

Post gate silicon germanium channel condensation and method for producing the same

GLOBALFOUNDRIES INC0 citations51

US10056381B2Aug 21, 2018

Punchthrough stop layers for fin-type field-effect transistors

GLOBALFOUNDRIES INC0 citations42

US10050119B2Aug 14, 2018

Method for late differential SOI thinning for improved FDSOI performance and HCI optimization

GLOBALFOUNDRIES INC0 citations40

GLOBALFOUNDRIES US INC

8 patents

US12560762B2Feb 24, 2026

Reflectors for a photonics chip

GLOBALFOUNDRIES US INC0 citations62

US12176351B2Dec 24, 2024

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

GLOBALFOUNDRIES US INC0 citations62

US11569268B1Jan 31, 2023

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

GLOBALFOUNDRIES US INC0 citations62

US11650382B1May 16, 2023

Optical components undercut by a sealed cavity

GLOBALFOUNDRIES US INC1 citations60

US11217678B2Jan 4, 2022

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

GLOBALFOUNDRIES US INC0 citations59

US11127843B2Sep 21, 2021

Sporer Ryan

GLOBALFOUNDRIES INC

Post gate silicon germanium channel condensation and method for producing the same

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Spacer defined fin growth and differential fin width

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Technique for patterning active regions of transistor elements in a late manufacturing stage

Post gate silicon germanium channel condensation and method for producing the same

Punchthrough stop layers for fin-type field-effect transistors

Method for late differential SOI thinning for improved FDSOI performance and HCI optimization

GLOBALFOUNDRIES US INC

Reflectors for a photonics chip

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Optical components undercut by a sealed cavity

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Asymmetrical lateral heterojunction bipolar transistors

Lateral heterojunction bipolar transistors with asymmetric junctions

Cladding structure in the back end of line of photonics chips