Inventor
COMBS JONATHAN
US15 patents
⚠️ This page may combine multiple inventors who share the name “COMBS JONATHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS12190157B2Jan 7, 2025
Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processor
INTEL CORP2 citations63
US12229034B2Feb 18, 2025
Device, system and method for identifying a source of latency in pipeline circuitry
INTEL CORP0 citations61
US9098284B2Aug 4, 2015
Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
INTEL CORP2 citations61
US11907712B2Feb 20, 2024
Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipeline
INTEL CORP1 citations56
US12536086B2Jan 27, 2026
System, method and apparatus for high level microarchitecture event performance monitoring using fixed counters
INTEL CORP0 citations54
US12288072B2Apr 29, 2025
Methods, systems, and apparatuses for precise last branch record event logging
INTEL CORP0 citations52
US10579492B2Mar 3, 2020
Device, system and method for identifying a source of latency in pipeline circuitry
INTEL CORP0 citations51
US12423103B2Sep 23, 2025
Instruction decode cluster offlining
INTEL CORP0 citations50
US8904112B2Dec 2, 2014
Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
INTEL CORP0 citations50
US12254319B2Mar 18, 2025
Scalable toggle point control circuitry for a clustered decode pipeline
INTEL CORP0 citations49
US12353881B2Jul 8, 2025
Circuitry and methods for power efficient generation of length markers for a variable length instruction set
INTEL CORP0 citations45
US12093694B2Sep 17, 2024
Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders
INTEL CORP0 citations45