Inventor
DURBHA ANANTH
US17 patents
⚠️ This page may combine multiple inventors who share the name “DURBHA ANANTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUADRIC IO INC
8 patentsUS10997115B2May 4, 2021
Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit
QUADRIC IO INC5 citations83
US10365860B1Jul 30, 2019
Machine perception and dense algorithm integrated circuit
QUADRIC IO INC7 citations83
US11086574B2Aug 10, 2021
Machine perception and dense algorithm integrated circuit
QUADRIC IO INC2 citations72
US11803508B2Oct 31, 2023
Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit
QUADRIC IO INC0 citations61
US11449459B2Sep 20, 2022
Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit
QUADRIC IO INC0 citations61
US10761848B1Sep 1, 2020
Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit
QUADRIC IO INC1 citations61
US10642541B2May 5, 2020
Machine perception and dense algorithm integrated circuit
QUADRIC IO INC0 citations51
US10474398B2Nov 12, 2019
Machine perception and dense algorithm integrated circuit
QUADRIC IO INC0 citations51
DURBHA ANANTH
5 patentsUS8572544B2Oct 29, 2013
Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization
DURBHA ANANTH5 citations82
US8276107B2Sep 25, 2012
Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
DURBHA ANANTH2 citations61
US8561005B2Oct 15, 2013
Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design
DURBHA ANANTH4 citations60
US8185862B2May 22, 2012
Architectural level power-aware optimization and risk mitigation
DURBHA ANANTH4 citations60
US8516416B1Aug 20, 2013
Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
DURBHA ANANTH3 citations58