Inventor
RAGHUNATHAN SHESHASHAYEE K
IN5 patents
Patents
5 patentsUS9798843B2Oct 24, 2017
Statistical timing using macro-model considering statistical timing value entry
IBM2 citations71
US10891412B1Jan 12, 2021
Offline analysis of hierarchical electronic design automation derived data
IBM1 citations54
US12547802B2Feb 10, 2026
Recommending changes in the design of an integrated circuit using a rules-based analysis of failures
IBM0 citations42
US9710594B2Jul 18, 2017
Variation-aware timing analysis using waveform construction
IBM0 citations40
US10671782B2Jun 2, 2020
Architecture for ordered write of data collected in parallel
IBM0 citations27