Inventor
DAVID HOWARD S
US28 patents
⚠️ This page may combine multiple inventors who share the name “DAVID HOWARD S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6795899B2Sep 21, 2004
Memory system with burst length shorter than prefetch length
INTEL CORP208 citations99
US7036053B2Apr 25, 2006
Two dimensional data eye centering for source synchronous data transfers
INTEL CORP63 citations95
US6925534B2Aug 2, 2005
Distributed memory module cache prefetch
INTEL CORP32 citations92
US6865646B2Mar 8, 2005
Segmented distributed memory module cache
INTEL CORP32 citations92
US6832177B2Dec 14, 2004
Method of addressing individual memory devices on a memory module
INTEL CORP42 citations92
US6026460AFeb 15, 2000
Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency
INTEL CORP40 citations92
US5668949ASep 16, 1997
System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
INTEL CORP19 citations92
US5537640AJul 16, 1996
Asynchronous modular bus architecture with cache consistency
INTEL CORP35 citations92
US7864604B2Jan 4, 2011
Multiple address outputs for programming the memory register set differently for different DRAM devices
INTEL CORP15 citations84
US7389387B2Jun 17, 2008
Distributed memory module cache writeback
INTEL CORP15 citations84
US6938129B2Aug 30, 2005
Distributed memory module cache
INTEL CORP12 citations84
US6931505B2Aug 16, 2005
Distributed memory module cache command formatting
INTEL CORP9 citations74
US5437021AJul 25, 1995
Programmable dedicated timer operating on a clock independent of processor timer
INTEL CORP14 citations73
US7188208B2Mar 6, 2007
Side-by-side inverted memory address and command buses
INTEL CORP9 citations70
US7392339B2Jun 24, 2008
Partial bank DRAM precharge
INTEL CORP5 citations63
US6880044B2Apr 12, 2005
Distributed memory module cache tag look-up
INTEL CORP6 citations63
US7626884B2Dec 1, 2009
Optimizing mode register set commands
INTEL CORP3 citations62
US6976121B2Dec 13, 2005
Apparatus and method to track command signal occurrence for DRAM data transfer
INTEL CORP5 citations62
US5590289ADec 31, 1996
Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources
INTEL CORP6 citations62
US8375241B2Feb 12, 2013
Method and system to improve the operations of a registered memory module
INTEL CORP1 citations52
US6976120B2Dec 13, 2005
Apparatus and method to track flag transitions for DRAM data transfer
INTEL CORP0 citations52
DAVID HOWARD S
4 patentsUS8327172B2Dec 4, 2012
Adaptive memory frequency scaling
DAVID HOWARD S7 citations83
US8412479B2Apr 2, 2013
Memory power estimation by means of calibrated weights and activity counters
DAVID HOWARD S6 citations72
US8438410B2May 7, 2013
Memory power management via dynamic memory operation states
DAVID HOWARD S5 citations71
US8738937B2May 27, 2014
Method and apparatus to limit memory power
DAVID HOWARD S3 citations61