Inventor
CHEN SEN-FU
TW18 patents
Patents
18 patentsUS6001538ADec 14, 1999
Damage free passivation layer etching process
TAIWAN SEMICONDUCTOR MFG72 citations93
US6380030B1Apr 30, 2002
Implant method for forming Si3N4 spacer
TAIWAN SEMICONDUCTOR MFG25 citations92
US6093629AJul 25, 2000
Method of simplified contact etching and ion implantation for CMOS technology
TAIWAN SEMICONDUCTOR MFG24 citations92
US5639342AJun 17, 1997
Method of monitoring and controlling a silicon nitride etch step
TAIWAN SEMICONDUCTOR MFG26 citations92
US6682659B1Jan 27, 2004
Method for forming corrosion inhibited conductor layer
TAIWAN SEMICONDUCTOR MFG57 citations91
US6627971B1Sep 30, 2003
Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates
TAIWAN SEMICONDUCTOR MFG21 citations91
US6394104B1May 28, 2002
Method of controlling and improving SOG etchback etcher
TAIWAN SEMICONDUCTOR MFG23 citations91
US6071826AJun 6, 2000
Method of manufacturing CMOS image sensor leakage free with double layer spacer
TAIWAN SEMICONDUCTOR MFG38 citations90
US5904570AMay 18, 1999
Method for polymer removal after etching
TAIWAN SEMICONDUCTOR MFG17 citations83
US6624466B2Sep 23, 2003
Implant method for forming Si3N4 spacer
TAIWAN SEMICONDUCTOR MFG7 citations73
US6232172B1May 15, 2001
Method to prevent auto-doping induced threshold voltage shift
TAIWAN SEMICONDUCTOR MFG7 citations73
US6162584ADec 19, 2000
Method of fabricating polysilicon structures with different resistance values for gate electrodes, resistors and capacitor plates in an integrated circuit
TAIWAN SEMICONDUCTOR MFG14 citations73
US6143474ANov 7, 2000
Method of fabricating polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates
TAIWAN SEMICONDUCTOR MFG7 citations72
US6077776AJun 20, 2000
Polysilicon residue free process by thermal treatment
TAIWAN SEMICONDUCTOR MFG9 citations72
US5719087AFeb 17, 1998
Process for bonding pad protection from damage
TAIWAN SEMICONDUCTOR MFG15 citations71
US6211031B1Apr 3, 2001
Method to produce dual polysilicon resistance in an integrated circuit
TAIWAN SEMICONDUCTOR MFG11 citations68
US5763316AJun 9, 1998
Substrate isolation process to minimize junction leakage
TAIWAN SEMICONDUCTOR MFG6 citations61
US6320269B1Nov 20, 2001
Method for preparing a semiconductor wafer to receive a protective tape
TAIWAN SEMICONDUCTOR MFG6 citations60