Inventor

GOLLIVER ROGER A

US33 patents

⚠️ This page may combine multiple inventors who share the name “GOLLIVER ROGER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOLLIVER ROGER A

INTEL CORP

Controlling access to multiple isolated memories in an isolated execution environment

Controlling access to multiple memory zones in an isolated execution environment

Executing isolated mode instructions in a secure system running in privilege rings

Protecting software environment in isolated execution

Platform and method for issuing and certifying a hardware-protected attestation key

Generating a key hieararchy for use in an isolated execution environment

Managing a secure environment using a chipset in isolated execution mode

Platform and method for remote attestation of a platform

Controlling accesses to isolated memory using a memory controller for isolated execution

Data manipulation instruction for enhancing value and efficiency of complex arithmetic

Scalar hardware for performing SIMD operations

Data manipulation instruction for enhancing value and efficiency of complex arithmetic

Synchronization of weakly ordered write combining operations using a fencing mechanism

Platform and method for remote attestation of a platform

Attestation key memory device and bus

File checking using remote signing authority via a network

Managing a secure environment using a chipset in isolated execution mode

Platform and method for generating and utilizing a protected audit log

Attestation key memory device and bus

Controlling access to multiple memory zones in an isolated execution environment

Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields

Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations

Protecting software environment in isolated execution

Generating isolated bus cycles for isolated execution

Managing accesses in a processor for isolated execution

Resetting a processor in an isolated execution environment

System for converting packed integer data into packed floating point data in reduced time

INST THE DEV OF EMERGING ARCHI

Method and apparatus for selectively controlling groups of registers

Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit

Emulating agent and method for reformatting computer instructions into a standard uniform format