Inventor

WILLIAMS DEREK EDWARD

US157 patents

⚠️ This page may combine multiple inventors who share the name “WILLIAMS DEREK EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILLIAMS DEREK EDWARD

IBM

High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

Speculative execution of instructions and processes before completion of preceding barrier operations

Multi-level multiprocessor speculation mechanism

Multiprocessor speculation mechanism via a barrier speculation flag

Demand-based larx-reserve protocol for SMP system buses

Method and system for counting events within a simulation model

Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction

Multiprocessor speculation mechanism for efficiently managing multiple barrier operations

System and method for asynchronously overlapping storage barrier operations with old and new storage operations

Method and system for run-time logic verification of operations in digital systems

Eviction override for larx-reserved addresses

Method and system for transferring data between buses having differing ordering policies

Method and system for instrumenting simulation models

Method and system for selectively disabling simulation model instrumentation

Processor and data processing system employing a variable store gather window

Method for priority scheduling and priority dispatching of store conditional operations in a store queue

Method, system and program product providing a configuration specification language having clone latch support

Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities

Processor, method, and data processing system employing a variable store gather window

Cache memory direct intervention

Method, system and program product providing a configuration specification language having split latch support

Processor, data processing system and method for synchronizing access to data in shared memory

Method, system and program product for specifying and using register entities to configure a simulated or physical digital system

Processor, data processing system and method for synchronizing access to data in shared memory

Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs

System and method for exposing hidden events on system buses

High performance symmetric multiprocessing systems via super-coherent data mechanisms

Symmetric multiprocessor systems with an independent super-coherent cache directory

Data processing system and method for resolving a conflict between requests to modify a shared cache line

System and method for providing multiprocessor speculation within a speculative branch path

Mechanism for folding storage barrier operations in a multiprocessor system

Dynamic hardware and software performance optimizations for super-coherent SMP systems

Super-coherent data mechanisms for shared caches in a multiprocessing system

Multiprocessor speculation mechanism with imprecise recycling of storage operations

Method and system for run-time logic verification of operations in digital systems in response to a plurality of parameters

Demand-based issuance of cache operations to a system bus

Demand based sync bus operation

Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies

Demand based sync bus operation

Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries

Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities

Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights

Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities

Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language

C-API instrumentation for HDL models

Method, system and program product for configuring a simulation model of a digital design

Dynamic loading of C-API HDL model instrumentation

Count data access in a distributed simulation environment

INTERNAT BUSINESS MACHNIES COR

Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system