Inventor
YAVOICH BRIAN J
US5 patents
Patents
5 patentsUS9997218B2Jun 12, 2018
Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
IBM0 citations50
US9792967B1Oct 17, 2017
Managing semiconductor memory array leakage current
IBM1 citations50
US9786339B2Oct 10, 2017
Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
IBM1 citations50
US9761289B1Sep 12, 2017
Managing semiconductor memory array leakage current
IBM0 citations50
US9583211B1Feb 28, 2017
Incorporating bit write capability with column interleave write enable and column redundancy steering
IBM0 citations45