Inventor
CHAKRAVARTI ASHIMA B
US32 patents
⚠️ This page may combine multiple inventors who share the name “CHAKRAVARTI ASHIMA B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS7595010B2Sep 29, 2009
Method for producing a doped nitride film, doped oxide film and other doped films
IBM57 citations97
US7361611B2Apr 22, 2008
Doped nitride film, doped oxide film and other doped films
IBM55 citations97
US7001844B2Feb 21, 2006
Material for contact etch layer to enhance device performance
IBM74 citations97
US6838695B2Jan 4, 2005
CMOS device structure with improved PFET gate electrode
IBM74 citations95
US6077786AJun 20, 2000
Methods and apparatus for filling high aspect ratio structures with silicate glass
IBM57 citations95
US6436760B1Aug 20, 2002
Method for reducing surface oxide in polysilicon processing
IBM23 citations92
US6500772B2Dec 31, 2002
Methods and materials for depositing films on semiconductor substrates
IBM40 citations88
US5643640AJul 1, 1997
Fluorine doped plasma enhanced phospho-silicate glass, and process
IBM20 citations88
US6159870ADec 12, 2000
Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill
IBM16 citations83
US6528383B1Mar 4, 2003
Simultaneous formation of deep trench capacitor and resistor
IBM14 citations80
US7759213B2Jul 20, 2010
Pattern independent Si:C selective epitaxy
IBM3 citations63
US6555166B2Apr 29, 2003
Method for reducing the microloading effect in a chemical vapor deposition reactor
IBM6 citations63
US6429149B1Aug 6, 2002
Low temperature LPCVD PSG/BPSG process
IBM6 citations63
US7838932B2Nov 23, 2010
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
IBM1 citations52
US7687804B2Mar 30, 2010
Method for fabricating a semiconductor structures and structures thereof
IBM1 citations52
US7473594B2Jan 6, 2009
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
IBM1 citations52
US7767579B2Aug 3, 2010
Protection of SiGe during etch and clean operations
IBM1 citations51
US7232774B2Jun 19, 2007
Polycrystalline silicon layer with nano-grain structure and method of manufacture
IBM0 citations50
US7888241B2Feb 15, 2011
Selective deposition of germanium spacers on nitride
IBM0 citations48
US7776624B2Aug 17, 2010
Method for improving semiconductor surfaces
IBM0 citations36
CHAKRAVARTI ASHIMA B
5 patentsUS8173524B1May 8, 2012
Process for epitaxially growing epitaxial material regions
CHAKRAVARTI ASHIMA B6 citations72
US8900961B2Dec 2, 2014
Selective deposition of germanium spacers on nitride
CHAKRAVARTI ASHIMA B3 citations62
US8389352B2Mar 5, 2013
Silicon germanium film formation method and structure
CHAKRAVARTI ASHIMA B0 citations51
US8563446B2Oct 22, 2013
Technique to create a buried plate in embedded dynamic random access memory device
CHAKRAVARTI ASHIMA B0 citations46
US8236710B2Aug 7, 2012
Technique to create a buried plate in embedded dynamic random access memory device
CHAKRAVARTI ASHIMA B0 citations46
BEDELL STEPHEN W
2 patentsUS8575655B2Nov 5, 2013
Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
BEDELL STEPHEN W9 citations84
US8440547B2May 14, 2013
Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
BEDELL STEPHEN W3 citations63