P

Inventor

LIN JENG-PING

TW33 patents
⚠️ This page may combine multiple inventors who share the name “LIN JENG-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NANYA TECHNOLOGY CORP

28 patents
US6734066B2May 11, 2004

Method for fabricating split gate flash memory cell

NANYA TECHNOLOGY CORP62 citations96
US6800895B2Oct 5, 2004

Vertical split gate flash memory cell and method for fabricating the same

NANYA TECHNOLOGY CORP21 citations92
US6794250B2Sep 21, 2004

Vertical split gate flash memory cell and method for fabricating the same

NANYA TECHNOLOGY CORP25 citations92
US6696717B2Feb 24, 2004

Memory cell with vertical transistor and trench capacitor

NANYA TECHNOLOGY CORP20 citations92
US8343829B2Jan 1, 2013

Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same

NANYA TECHNOLOGY CORP24 citations91
US7994559B2Aug 9, 2011

Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same

NANYA TECHNOLOGY CORP23 citations91
US6432774B2Aug 13, 2002

Method of fabricating memory cell with trench capacitor and vertical transistor

NANYA TECHNOLOGY CORP30 citations90
US6355529B2Mar 12, 2002

Method of fabricating memory cell with vertical transistor

NANYA TECHNOLOGY CORP23 citations90
US6534359B2Mar 18, 2003

Method of fabricating memory cell

NANYA TECHNOLOGY CORP13 citations82
US7678692B2Mar 16, 2010

Fabrication method for a damascene bit line contact plug

NANYA TECHNOLOGY CORP6 citations74
US7541244B2Jun 2, 2009

Semiconductor device having a trench gate and method of fabricating the same

NANYA TECHNOLOGY CORP6 citations74
US11315928B2Apr 26, 2022

Semiconductor structure with buried power line and buried signal line and method for manufacturing the same

NANYA TECHNOLOGY CORP4 citations73
US10090154B1Oct 2, 2018

Method for preparing a semiconductor structure having second line patterns and third line patterns formed over first line patterns

NANYA TECHNOLOGY CORP2 citations73
US6781181B2Aug 24, 2004

Layout of a folded bitline DRAM with a borderless bitline

NANYA TECHNOLOGY CORP8 citations71
US7759190B2Jul 20, 2010

Memory device and fabrication method thereof

NANYA TECHNOLOGY CORP4 citations63
US7109094B2Sep 19, 2006

Method for preventing leakage in shallow trench isolation

NANYA TECHNOLOGY CORP4 citations63
US7005698B2Feb 28, 2006

Split gate flash memory cell

NANYA TECHNOLOGY CORP3 citations63
US6919245B2Jul 19, 2005

Dynamic random access memory cell layout and fabrication method thereof

NANYA TECHNOLOGY CORP2 citations63
US11647623B2May 9, 2023

Method for manufacturing semiconductor structure with buried power line and buried signal line

NANYA TECHNOLOGY CORP0 citations62
US6801462B2Oct 5, 2004

Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices

NANYA TECHNOLOGY CORP5 citations62
US6743717B1Jun 1, 2004

Method for forming silicide at source and drain

NANYA TECHNOLOGY CORP4 citations62
US6909136B2Jun 21, 2005

Trench-capacitor DRAM cell having a folded gate conductor

NANYA TECHNOLOGY CORP3 citations60
US6788598B2Sep 7, 2004

Test key for detecting overlap between active area and deep trench capacitor of a DRAM and detection method thereof

NANYA TECHNOLOGY CORP3 citations60
US7144799B2Dec 5, 2006

Method for pre-retaining CB opening

NANYA TECHNOLOGY CORP3 citations59
US7622770B2Nov 24, 2009

Semiconductor device having a trench gate and method of fabricating the same

NANYA TECHNOLOGY CORP0 citations52
US7285377B2Oct 23, 2007

Fabrication method for a damascene bit line contact plug

NANYA TECHNOLOGY CORP0 citations52
US6958521B2Oct 25, 2005

Shallow trench isolation structure

NANYA TECHNOLOGY CORP0 citations52
US9779957B2Oct 3, 2017

Method of manufacturing independent depth-controlled shallow trench isolation

NANYA TECHNOLOGY CORP0 citations39

DELTA ELECTRONICS INC

3 patents

UNITED MICROELECTRONICS CORP

1 patent

HO HSIN-JUNG

1 patent