Inventor

WEBER CORY E

US37 patents

⚠️ This page may combine multiple inventors who share the name “WEBER CORY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEBER CORY E

INTEL CORP

Indium-boron dual halo MOSFET

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Epitaxial silicon germanium for reduced contact resistance in field-effect transistors

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Epitaxial silicon germanium for reduced contact resistance in field-effect transistors

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Backside fin recess control with multi-hsi option

Hybrid trigate and nanowire CMOS device architecture

Nanowire structures having wrap-around contacts

High concentration indium fluorine retrograde wells

High concentration indium fluorine retrograde wells

Reduced leakage trench isolation

Reduced leakage trench isolation

Backside fin recess control with multi-HSI option

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Semiconductor nanowire device having (111)-plane channel sidewalls

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Contacts to n-type transistors with X-valley layer over L-valley channels

Semiconductor nanowire device having (111)-plane channel sidewalls

Methods of doping fin structures of non-planar transistor devices

Methods of doping fin structures of non-planar transistor devices

Techniques for increasing channel region tensile strain in n-MOS devices

Memory arrays with backside components and angled transistors

Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing

Source/drain regions in integrated circuit structures

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Semiconductor device having metallic source and drain regions

Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices

Reducing off-state leakage in semiconductor devices

Extension of nanocomb transistor arrangements to implement gate all around

Enhanced dislocation stress transistor

Enhanced dislocation stress transistor

Enhanced dislocation stress transistor

GILES MARTIN D

Semiconductor device having metallic source and drain regions

CEA STEPHEN M

Nanowire structures having wrap-around contacts

GOOGLE LLC

Nanowire structures having wrap-around contacts