Inventor

WANG YING LANG

TW156 patents

⚠️ This page may combine multiple inventors who share the name “WANG YING LANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG YING LANG

TAIWAN SEMICONDUCTOR MFG

Self-aligned method for forming dual gate thin film transistor (TFT) device

Three-dimensional type inductor for mixed mode radio frequency device

Methods to improve copper-fluorinated silica glass interconnects

Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue

Chemical mechanical polishing slurry

Process for cleaning a semiconductor substrate after chemical-mechanical polishing

Metal surface and film protection method to prolong Q-time after metal deposition

Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure

Method to solve particle performance of FSG layer by using UFU season film for FSG process

Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer

PE-silane oxide particle performance improvement

Methods to reduce metal bridges and line shorts in integrated circuits

Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry

CMP process leaving no residual oxide layer or slurry particles

Method of manufacturing a very deep STI (shallow trench isolation)

Method and system for virtual metrology in semiconductor manufacturing

Removal of SiON residue after CMP

Shallow trench isolation process

Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof

Method for capping over a copper layer

Metal shield structure and methods for BSI image sensors

Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current

Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film

Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits

Use of a capping layer to reduce particle evolution during sputter pre-clean procedures

Semiconductor chamber process apparatus and method

Method for reducing defects in post passivation interconnect process

Preventative maintenance aided tool for CVD chamber

Current-leveling electroplating/electropolishing electrode

Method for cleaning a plasma enhanced CVD chamber

Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing

Reduction of tungsten damascene residue

Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity

TAIWAN SEMICONDUCTOR MFG CO LTD

Field effect transistor contact with reduced contact resistance using implantation process

Source/drain structure

Electrode structure to improve RRAM performance

Method for controlling chemical mechanical polishing process

Semiconductor device and fabricating method thereof

Source/drain structure

Melt anneal source and drain regions

Bonding pad on a back side illuminated image sensor

Field effect transistor contact with reduced contact resistance using implantation process

Wafer edge trimming tool using abrasive tape

Semiconductor device and manufacturing method thereof

CHEN KEI-WEI

Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process

CHANG SHIH-CHIEH

Via/contact and damascene structures and manufacturing methods thereof

KUO CHUN-TING

Methods for minimizing edge peeling in the manufacturing of BSI chips

CHANG TING-CHANG

Methods and apparatus for resistive random access memory (RRAM)

HSIAO WEN CHU

Method of manufacturing semiconductor device

NIAN JUN-NAN

Semiconductor device and method of formation