Inventor

FRIED DAVID M

US67 patents

⚠️ This page may combine multiple inventors who share the name “FRIED DAVID M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FRIED DAVID M

IBM

Concurrent Fin-FET and thick-body device fabrication

Strained Fin FETs structure and method

Method for fabricating multiple-plane FinFET CMOS

FinFET layout generation

Multiple-plane FinFET CMOS

FinFET CMOS with NVRAM capability

Strained fin FETs structure and method

Double gated transistor and method of fabrication

FinFET SRAM cell using low mobility plane for cell stability and method for forming

Finfet SRAM cell using low mobility plane for cell stability and method for forming

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Strained fin FETs structure and method

Fin FET devices from bulk semiconductor and method for forming

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Implanted asymmetric doped polysilicon gate FinFET

Dual double gate transistor

Fin memory cell and method of fabrication

Integrated antifuse structure for FINFET and CMOS devices

Integrated circuit having pairs of parallel complementary FinFETs

Dual double gate transistor and method for forming

Implanted asymmetric doped polysilicon gate FinFET

Fin-type resistors

Formation of capacitor having a Fin structure

FinFET CMOS with NVRAM capability

Integrated circuit with capacitors having a fin structure

Integrated circuit having pairs of parallel complementary FinFETs

Fin-type resistors

Double gated transistor and method of fabrication

Double gated vertical transistor with different first and second gate materials

DRAM cell with enhanced SER immunity

Method and system for including parametric in-line test data in simulations for improved model to hardware correlation

Computation of supply chain planning process efficiency

Method and structure for self-aligned device contacts

Semiconductor structure and system for fabricating an integrated circuit chip

DRAM cell with enhanced SER immunity

Method and structure for self-aligned device contacts

Area-efficient gated diode structure and method of forming same

Semiconductor structure with self-aligned device contacts

COVENTOR INC

System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment

Rule checks in 3-D virtual fabrication environment

System and method for performing directed self-assembly in a 3-D virtual fabrication environment

Predictive 3-D virtual fabrication system and method

Modeling pattern dependent effects for a 3-D virtual semiconductor fabrication environment

System and method for modeling epitaxial growth in a 3-D virtual fabrication environment

Multi-etch process using material-specific behavioral parameters in 3-D virtual fabrication environment

System and method for performing process model calibration in a virtual semiconductor device fabrication environment

System and method for electrical behavior modeling in a 3D virtual fabrication environment

FRIED DAVID M

FET structures with trench implantation to improve back channel leakage and body resistance

FET structures with trench implantation to improve back channel leakage and body resistance

LAM RES CORP

Fill process optimization using feature scale modeling