Inventor

SECATCH STACEY

US39 patents

⚠️ This page may combine multiple inventors who share the name “SECATCH STACEY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SECATCH STACEY

SEAGATE TECHNOLOGY LLC

Background reads to condition programmed semiconductor memory cells

Storage compute appliance with internal data encryption

Encryption key shredding to protect non-persistent data

Balanced die set execution in a data storage system

Global pool of garbage collection units (GCUs) in a shared non-volatile memory device

Encrypting system level data structures

Deterministic optimization via performance tracking in a data storage system

Background reads to condition programmed semiconductor memory cells

Configurable mapping system in a non-volatile memory

Optimization of reference voltages in a non-volatile memory (NVM)

Enhanced read recovery based on write time information

Collection of uncorrelated entropy during a power down sequence

Data storage system with strategic contention avoidance

Encryption key shredding to protect non-persistent data

Semiconductor die failure recovery in a data storage device

Staggered garbage collection unit (GCU) allocation across dies

Secondary key allocation to storage drive failure domains

Data storage system with workload-based asymmetry compensation

Data storage system with workload-based dynamic power consumption

Storage compute appliance with user authentication and memory allocation capabilities

Enhanced read recovery based on write time information

Staggered garbage collection unit (GCU) allocation across dies

Hash authenticated data

XILINX INC

Token ecosystem for buffer management

Methods of mapping a logical memory representation to physical memory in a programmable logic device

Method and apparatus for providing a channelized buffer

Dynamic core pipeline

Dynamic timer for testbench interface synchronization

Two-pass method for implementing a flexible testbench

Queue for simplified communication within a multithreaded testbench

Binary priority encoder

Methods of generating a design architecture tailored to specified requirements of a PLD design

Two-pass method for implementing a flexible testbench

AGILENT TECHNOLOGIES INC

Pushback FIFO

Metal programmable clock distribution for integrated circuits

Method and apparatus for hierarchical clock tree analysis

ROHRER CARL F

Method and apparatus for processing data in an embedded system

Method and apparatus for providing egress data in an embedded system

AVAGO TECHNOLOGIES GENERAL IP

Pushback FIFO