Inventor

KURD NASSER A

US59 patents

⚠️ This page may combine multiple inventors who share the name “KURD NASSER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KURD NASSER A

INTEL CORP

Adaptive frequency clock signal

Signal synchronization and frequency synthesis system configurable as PLL or DLL

Method and apparatus for detecting on-die voltage variations

Multiple VCO phase lock loop architecture

Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

Glitch protection and detection for strobed data

Parallel phase locked loops skew measure and dynamic skew and jitter error compensation method and apparatus

Self-biasing sense amplifier

Frequency management apparatus, systems, and methods

Method and apparatus for detecting on-die voltage variations

Adaptive frequency clock generation system

Automated clock alignment for testing processors in a bypass mode

Digital clock skew detection and phase alignment

High frequency system with duty cycle buffer

Method of providing and circuit for providing phase lock loop frequency overshoot control

Apparatus and method for fast phase locking for digital phase locked loop

Circuit for I/O clock generation

Frequency overshoot and voltage droop mitigation apparatus and method

Method and apparatus for switched adaptive clocking

Apparatus for power consumption reduction

PLL with controlled VCO bias

Clock signal generation and distribution via ring oscillators

Clock enable generation, synchronization, and distribution

Circuit to manage and lower clock inaccuracies of integrated circuits

Scan cell designs for a double-edge-triggered flip-flop

Clock phase compensation apparatus and method

Adjusting PLL/analog supply to track CPU core supply through a voltage regulator

Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop

Apparatus for dynamically adapting a clock generator with respect to changes in power supply

PLL with controllable bias level

Glitch protection and detection for strobed data

Method for power consumption reduction

High frequency system with duty cycle buffer

Self-referenced droop detector circuitry

Self-referenced droop detector circuitry

Monitor circuitry for power management and transistor aging tracking

Methods and devices for dynamically avoiding radio frequency interference

Data and clock synchronization and variation compensation apparatus and method

Frequency overshoot and voltage droop mitigation apparatus and method

Frequency overshoot and voltage droop mitigation apparatus and method

Apparatus to improve lock time of a frequency locked loop

Measuring a characteristic of an integrated circuit

Monitor circuitry for power management and transistor aging tracking

Method and apparatus for fast wake-up of analog biases

Clock generation system

Integrated MEMS resonator and method

KURD NASSER A

Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces

System and method for scaling power of a phase-locked loop architecture

NEIDENGARD MARK L

Frequency synthesis methods and systems

MOSALIKANTI PRAVEEN

Methods and apparatuses for delay-locked loops and phase-locked loops