Inventor

BARKATULLAH JAVED S

US21 patents

⚠️ This page may combine multiple inventors who share the name “BARKATULLAH JAVED S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARKATULLAH JAVED S

INTEL CORP

Adaptive frequency clock signal

Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit

Core clock correction in a 2/N mode clocking scheme

Method and apparatus for detecting on-die voltage variations

Method and apparatus for clock skew compensation

Method and apparatus for detecting on-die voltage variations

Adaptive frequency clock generation system

Method and apparatus for correcting a clock duty cycle in a clock distribution network

Automated clock alignment for testing processors in a bypass mode

Core clock correction in a 2/n mode clocking scheme

PLL with controlled VCO bias

Clock signal generation and distribution via ring oscillators

Circuit to manage and lower clock inaccuracies of integrated circuits

Generating a 2-phase clock using a non-50% divider circuit

Method and apparatus for generating 2/N mode bus clock signals

Core clock correction in a 2/N mode clocking scheme

Smart buffer circuit to match a delay over a range of loads

Method and apparatus for generating 2/N mode bus clock signals

EVERSPIN TECHNOLOGIES INC

Delayed write-back in memory

Delayed write-back in memory

Delayed write-back in memory