Inventor

ARIMILLI LAKSHMINARAYANA B

US67 patents

⚠️ This page may combine multiple inventors who share the name “ARIMILLI LAKSHMINARAYANA B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMILLI LAKSHMINARAYANA B

IBM

System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture

Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture

Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture

Direct memory access between an accelerator and a processor using a coherency adapter

Push instruction for pushing a message payload from a sending thread to a receiving thread

Hardware-assisted interthread push communication

Hardware-assisted interthread push communication

Partial cache line accesses based on memory access patterns

Dynamic selection of a memory access size

Mechanism to provide reliability through packet drop detection

Mechanism to perform debugging of global shared memory (GSM) operations

Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture

Mechanism to provide software guaranteed reliability for GSM operations

Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips

System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture

Managing lowest point of coherency (LPC) memory using a service layer adapter

Direct memory access between an accelerator and a processor using a coherency adapter

Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread

Addressing for inter-thread push communication

Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture

Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture

System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture

System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture

System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture

Memory move instruction sequence targeting an accelerator switchboard

Direct memory access between an accelerator and a processor using a coherency adapter

Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture

Live partition mobility enabled hardware accelerator address translation fault resolution

Managed hardware accelerator address translation fault resolution utilizing a credit

Live partition mobility enabled hardware accelerator address translation fault resolution

ARIMILLI LAKSHMINARAYANA B

Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Hardware based dynamic load balancing of message passing interface tasks

Performing dynamic request routing based on broadcast queue depths

Host fabric interface (HFI) to perform global shared memory (GSM) operations

Hardware based dynamic load balancing of message passing interface tasks by modifying tasks

User level message broadcast mechanism in distributed computing environment

Method for data processing using a multi-tiered full-graph interconnect architecture

Cache management for partial cache line operations

Modifying an operation of one or more processors executing message passing interface tasks

Collective acceleration unit tree flow control and retransmit

Memory lock mechanism for a multiprocessor system

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Mechanism to prevent illegal access to task address space by unauthorized tasks

Notification to task of completion of GSM operations by initiator node

Generating and issuing global shared memory operations via a send FIFO

Guaranteeing delivery of multi-packet GSM messages

Claiming coherency ownership of a partial cache line of data

Interconnect operation indicating acceptability of partial data delivery

Collective acceleration unit tree structure