Inventor

ARIMILLI RAVI K

US151 patents

⚠️ This page may combine multiple inventors who share the name “ARIMILLI RAVI K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMILLI RAVI K

IBM

Convergence of air water cooling of an electronics rack and a computer room in a single unit

System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture

Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange

Coherency and synchronization mechanisms for I/O channel controllers in a data processing system

Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture

Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture

Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture

Specialized memory move barrier operations

Handling of address conflicts during asynchronous memory move operations

Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters

Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem

Address mapping mechanism for behavioral memory enablement within a data processing system

High performance cache intervention mechanism for symmetric multiprocessor systems

Enhanced cache management mechanism via an intelligent system bus monitor

Intelligent cache management mechanism via processor access sequence analysis

Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis

Wake-and-go mechanism with exclusive system bus response

Dual latency status and coherency reporting for a multiprocessing system

Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory

Computer system DMA transfer

Data transfer using bus address lines

High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device

Management of process-to-process intra-cluster communication requests

Reporting of partially performed memory move

ARIMILLI RAVI K

Partial cache line storage-modifying operation based upon a hint

Fully asynchronous memory mover

Hardware wake-and-go mechanism with look-ahead polling

Reassembling streaming data across multiple packetized communication channels

Hardware wake-and-go mechanism for a data processing system

Wake-and-go mechanism with system address bus transaction master

Programming idiom accelerator for remote update

Supporting multiple high bandwidth I/O controllers on a single chip

Cache management during asynchronous memory move operations

Asynchronous memory move across physical nodes with dual-sided communication

Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history

Sourcing differing amounts of prefetch data in response to data prefetch requests

Mechanisms for communicating with an asynchronous memory mover to perform AMM operations

Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system

Techniques for data prefetching using indirect addressing with offset

Techniques for indirect data prefetching

Virtual barrier synchronization cache

ARIMILLI LAKSHMINARAYANA B

Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Hardware based dynamic load balancing of message passing interface tasks

Performing dynamic request routing based on broadcast queue depths

Host fabric interface (HFI) to perform global shared memory (GSM) operations

Hardware based dynamic load balancing of message passing interface tasks by modifying tasks

User level message broadcast mechanism in distributed computing environment

Method for data processing using a multi-tiered full-graph interconnect architecture

Modifying an operation of one or more processors executing message passing interface tasks