Inventor

STARKE WILLIAM J

US203 patents

⚠️ This page may combine multiple inventors who share the name “STARKE WILLIAM J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STARKE WILLIAM J

IBM

Storage access authorization controls in a computer system using dynamic translation of large addresses

Method of using a target processor to execute programs of a source architecture that uses multiple address spaces

Register pipe for multi-processing engine environment

Efficient enforcement of barriers with respect to memory move sequences

Address mapping mechanism for behavioral memory enablement within a data processing system

High performance symmetric multiprocessing systems via super-coherent data mechanisms

Symmetric multiprocessor systems with an independent super-coherent cache directory

Dynamic hardware and software performance optimizations for super-coherent SMP systems

Super-coherent data mechanisms for shared caches in a multiprocessing system

Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state

Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality

Data processing system and method for efficient communication utilizing an in coherency state

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Method system and apparatus for instruction execution tracing with out of order processors

Integrated circuit and data processing system having a configurable cache directory for an accelerator

Counter-based victim selection in a cache memory

Counter-based victim selection in a cache memory

Push instruction for pushing a message payload from a sending thread to a receiving thread

Cache backing store for transactional memory

Hardware-assisted interthread push communication

Hardware-assisted interthread push communication

Transient condition management utilizing a posted error detection processing protocol

Virtual machines failover

Data cache block deallocate requests in a multi-level cache hierarchy

Allocating a global shared memory

Data processing system, method and interconnect fabric supporting multiple planes of processing nodes

Reducing number of rejected snoop requests by extending time to respond to snoop request

Protecting ownership transfer with non-uniform protection windows

Data processing system, cache system and method for reducing imprecise invalid coherency states

Fault tolerant encoding of directory states for stuck bits

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction

Behavioral memory mechanism for a data processing system

Behavioral memory enabled fetch prediction mechanism within a data processing system

Empirically based dynamic control of transmission of victim cache lateral castouts

Victim cache replacement

Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations

Store stream prefetching in a microprocessor

GUTHRIE GUY L

Processor performance improvement for instruction sequences that include barrier instructions

Cache-based speculation of stores following synchronizing operations

Cache-based speculation of stores following synchronizing operations

Lateral cache-to-cache cast-in

Victim cache line selection

ARIMILLI RAVI K

Partial cache line storage-modifying operation based upon a hint

Virtual barrier synchronization cache

CLARK LEO J

Data processing system and method for predictively selecting a scope of broadcast of an operation

Ticket-based operation tracking

CARGNONI ROBERT A

Load request scheduling in a cache hierarchy

GLOBALFOUNDRIES INC

Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold

ARIMILLI LAKSHMINARAYANA B

Host fabric interface (HFI) to perform global shared memory (GSM) operations