Inventor
MAKINENI SRIHARI
US26 patents
⚠️ This page may combine multiple inventors who share the name “MAKINENI SRIHARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
20 patentsUS8036246B2Oct 11, 2011
Packet coalescing
INTEL CORP12 citations92
US7725657B2May 25, 2010
Dynamic quality of service (QoS) for a shared cache
INTEL CORP33 citations92
US7620071B2Nov 17, 2009
Packet coalescing
INTEL CORP17 citations92
US7596662B2Sep 29, 2009
Selective storage of data in levels of a cache memory
INTEL CORP21 citations92
US7552288B2Jun 23, 2009
Selectively inclusive cache architecture
INTEL CORP19 citations92
US9047171B2Jun 2, 2015
Differentiating cache reliability to reduce minimum on-die voltage
INTEL CORP7 citations84
US7490191B2Feb 10, 2009
Sharing information between guests in a virtual machine environment
INTEL CORP11 citations83
US7895415B2Feb 22, 2011
Cache sharing based thread control
INTEL CORP16 citations82
US10652147B2May 12, 2020
Packet coalescing
INTEL CORP2 citations73
US10664039B2May 26, 2020
Power efficient processor architecture
INTEL CORP1 citations72
US9870047B2Jan 16, 2018
Power efficient processor architecture
INTEL CORP1 citations62
US9864427B2Jan 9, 2018
Power efficient processor architecture
INTEL CORP1 citations62
US12248783B2Mar 11, 2025
Frequency scaling for per-core accelerator assignments
INTEL CORP0 citations59
US11775298B2Oct 3, 2023
Frequency scaling for per-core accelerator assignments
INTEL CORP0 citations59
US11567556B2Jan 31, 2023
Platform slicing of central processing unit (CPU) resources
INTEL CORP0 citations59
US7525989B2Apr 28, 2009
System, method and device for time slot status messaging among SONET nodes
INTEL CORP4 citations58
US10095520B2Oct 9, 2018
Interrupt return instruction with embedded interrupt service functionality
INTEL CORP0 citations52
US10048743B2Aug 14, 2018
Power efficient processor architecture
INTEL CORP0 citations51
US9753732B2Sep 5, 2017
Embedded branch prediction unit
INTEL CORP0 citations50
US12348969B2Jul 1, 2025
Systems, methods, and apparatus for workload optimized central processing units (CPUS)
INTEL CORP0 citations47