Inventor
DOUR NAVNEET
US17 patents
Patents
17 patentsUS7432731B2Oct 7, 2008
Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
INTEL CORP67 citations97
US6563337B2May 13, 2003
Driver impedance control mechanism
INTEL CORP95 citations97
US7602859B2Oct 13, 2009
Calibrating integrating receivers for source synchronous protocol
INTEL CORP22 citations91
US7020818B2Mar 28, 2006
Method and apparatus for PVT controller for programmable on die termination
INTEL CORP30 citations91
US6236250B1May 22, 2001
Circuit for independent power-up sequencing of a multi-voltage chip
INTEL CORP15 citations84
US6617891B2Sep 9, 2003
Slew rate at buffers by isolating predriver from driver
INTEL CORP15 citations82
US7307900B2Dec 11, 2007
Method and apparatus for optimizing strobe to clock relationship
INTEL CORP8 citations73
US7012451B2Mar 14, 2006
Slew rate at buffers by isolating predriver from driver
INTEL CORP7 citations72
US11722128B2Aug 8, 2023
Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)
INTEL CORP2 citations70
US11070200B2Jul 20, 2021
Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)
INTEL CORP4 citations70
US11042315B2Jun 22, 2021
Dynamically programmable memory test traffic router
INTEL CORP0 citations62
US10613955B2Apr 7, 2020
Platform debug and testing with secured hardware
INTEL CORP1 citations62
US7403034B2Jul 22, 2008
PVT controller for programmable on die termination
INTEL CORP4 citations61
US6414539B1Jul 2, 2002
AC timings at the input buffer of source synchronous and common clock designs by making the supply for differential amplifier track the reference voltage
INTEL CORP4 citations61
US7751274B2Jul 6, 2010
Extended synchronized clock
INTEL CORP2 citations60
US7009894B2Mar 7, 2006
Dynamically activated memory controller data termination
INTEL CORP3 citations60
US7746135B2Jun 29, 2010
Wake-up circuit
INTEL CORP4 citations59