Inventor

ADAM THOMAS N

US110 patents

⚠️ This page may combine multiple inventors who share the name “ADAM THOMAS N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADAM THOMAS N

IBM

Strained SiGe nanowire having (111)-oriented sidewalls

Semiconductor substrate with multiple SiGe regions having different germanium concentrations by a single epitaxy process

FinFET and method of fabrication

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Borderless contacts for semiconductor transistors

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Prevention of fin erosion for semiconductor devices

Bulk finFET with controlled fin height and high-k liner

Epitaxial grown extremely shallow extension region

Raised source/drain and gate portion with dielectric spacer or air gap spacer

Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same

Multi-fin finFETs with merged-fin source/drains and replacement gates

Halo region formation by epitaxial growth

Raised source/drain and gate portion with dielectric spacer or air gap spacer

Formation of bulk SiGe fin with dielectric isolation by anodization

FinFET devices containing merged epitaxial Fin-containing contact regions

Device structure with increased contact area and reduced gate capacitance

Embedded source/drains with epitaxial oxide underlayer

Prevention of fin erosion for semiconductor devices

Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials

Stressed transistor with improved metastability

Strained semiconductor-on-insulator (sSOI) by a simox method

Mobility enhancement in SiGe heterojunction bipolar transistors

Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same

Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods

Strained semiconductor-on-insulator (sSOI) by a simox method

Vertical device with optimal trench shape

Semiconductor fabrication method using stop layer

Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials

Compressive strained III-V complementary metal oxide semiconductor (CMOS) device

ADAM THOMAS N

Semiconductor structure having a source and a drain with reverse facets

Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures

Merged fin finFET with (100) sidewall surfaces and method of making same

Thin heterostructure channel device

Strained channel for depleted channel semiconductor devices

Transistor with improved sigma-shaped embedded stressor and method of formation

Thin body semiconductor devices

Semiconductor structure having NFET extension last implants

Thin hetereostructure channel device

GLOBALFOUNDRIES INC

Semiconductor structure having a source and a drain with reverse facets

FinFET having an epitaxially grown semiconductor on the fin in the channel region

Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes

Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures

Semiconductor structure with aspect ratio trapping capabilities

KHAKIFIROOZ ALI

High density bulk fin capacitor

Selectively raised source/drain transistor

CHENG KANGGUO

Method and structure for forming fin resistors

Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts

REZNICEK ALEXANDER

Bulk finFET with controlled fin height and high-K liner