Inventor

HOLT JUDSON R

US156 patents

⚠️ This page may combine multiple inventors who share the name “HOLT JUDSON R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOLT JUDSON R

IBM

Ultra-thin body super-steep retrograde well (SSRW) FET devices

Metal oxide field effect transistor with a sharp halo

Chemical treatment to retard diffusion in a semiconductor overlayer

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

Transistor having V-shaped embedded stressor

High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods

Defect reduction with rotated double aspect ratio trapping

Single crystal source-drain merged by polycrystalline material

Halo region formation by epitaxial growth

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Stressed transistor with improved metastability

CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy

Method and structure to form self-aligned selective-SOI

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same

Hybrid orientation substrate and method for fabrication of thereof

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Uniform junction formation in FinFETs

finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Semiconductor device and method with greater epitaxial growth on 110 crystal plane

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Method for embedded diamond-shaped stress element

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Stressed field effect transistors on hybrid orientation substrate

GLOBALFOUNDRIES INC

Self-aligned sacrificial epitaxial capping for trench silicide

Junction butting structure using nonuniform trench shape

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Epitaxially grown silicon germanium channel FinFET with silicon underlayer

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Asymmetric semiconductor device and method of forming same

Recess liner for silicon germanium fin formation

FinFET device containing a composite spacer structure

Epitaxial growth of material on source/drain regions of FinFET structure

GLOBALFOUNDRIES US INC

Fin-based lateral bipolar junction transistor and method

Bipolar transistor structure on semiconductor fin and methods to form same

Heterojunction bipolar transistor

Silicided gate structures

Structure with substrate-embedded arrow waveguide and method

LIU YAOCHENG

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

CHAN KEVIN K

Field effect transistor device

Delta monolayer dopants epitaxy for embedded source/drain silicide

CHARTERED SEMICONDUCTOR MFG

Method to form selective strained Si using lateral epitaxy

BEDELL STEPHEN W

Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering

INFINEON TECHNOLOGIES AG

Strained semiconductor device and method of making same

HARLEY ERIC C T

Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure

ADAM THOMAS N

Stress enhanced transistor devices and methods of making