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Inventor
CHAN HSUN-CHANG
TW
2 patents
Patents
2 patents
US7026233B2
Apr 11, 2006
Method for reducing defects in post passivation interconnect process
TAIWAN SEMICONDUCTOR MFG
12 citations
81
US7528478B2
May 5, 2009
Semiconductor devices having post passivation interconnections and a buffer layer
TAIWAN SEMICONDUCTOR MFG
0 citations
49