Inventor

DENNARD ROBERT HEATH

US10 patents

⚠️ This page may combine multiple inventors who share the name “DENNARD ROBERT HEATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

7 patents

US6020581AFeb 1, 2000

Supply voltage independent bandgap based reference generator circuit for SOI/bulk CMOS technologies

IBM45 citations91

US6060905AMay 9, 2000

Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits

IBM18 citations83

US4035198AJul 12, 1977

Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

IBM21 citations78

US4090289AMay 23, 1978

Method of fabrication for field effect transistors (FETs) having a common channel stopper and FET channel doping with the channel stopper doping self-aligned to the dielectric isolation between FETS

IBM14 citations69

CHENG KANGGUO

2 patents

US8293615B2Oct 23, 2012

Self-aligned dual depth isolation and method of fabrication

CHENG KANGGUO11 citations84

US8587086B2Nov 19, 2013

Self-aligned dual depth isolation and method of fabrication

CHENG KANGGUO1 citations52

BICKFORD HARRY RANDALL

1 patent

US8604828B1Dec 10, 2013

Variable voltage CMOS off-chip driver and receiver circuits

BICKFORD HARRY RANDALL16 citations79

DENNARD ROBERT HEATH

IBM

Solid state CMOS imager using silicon-on-insulator or bulk silicon

Voltage level translation for an output driver system with a bias generator

Circuit and method for voltage level translation utilizing a bias generator

Supply voltage independent bandgap based reference generator circuit for SOI/bulk CMOS technologies

Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits

Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Method of fabrication for field effect transistors (FETs) having a common channel stopper and FET channel doping with the channel stopper doping self-aligned to the dielectric isolation between FETS

CHENG KANGGUO

Self-aligned dual depth isolation and method of fabrication

Self-aligned dual depth isolation and method of fabrication

BICKFORD HARRY RANDALL

Variable voltage CMOS off-chip driver and receiver circuits