Inventor
MOCUTA DAN M
US19 patents
⚠️ This page may combine multiple inventors who share the name “MOCUTA DAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS7723750B2May 25, 2010
MOSFET with super-steep retrograded island
IBM124 citations99
US6916698B2Jul 12, 2005
High performance CMOS device structure with mid-gap metal gate
IBM139 citations99
US7071103B2Jul 4, 2006
Chemical treatment to retard diffusion in a semiconductor overlayer
IBM120 citations97
US6958286B2Oct 25, 2005
Method of preventing surface roughening during hydrogen prebake of SiGe substrates
IBM238 citations97
US6762469B2Jul 13, 2004
High performance CMOS device structure with mid-gap metal gate
IBM68 citations96
US7268049B2Sep 11, 2007
Structure and method for manufacturing MOSFET with super-steep retrograded island
IBM21 citations92
US7691698B2Apr 6, 2010
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
IBM15 citations84
US7550370B2Jun 23, 2009
Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density
IBM11 citations84
US7528027B1May 5, 2009
Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
IBM12 citations84
US7498602B2Mar 3, 2009
Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets
IBM5 citations74
US7202132B2Apr 10, 2007
Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
IBM9 citations74
US9093275B2Jul 28, 2015
Multi-height multi-composition semiconductor fins
IBM6 citations73
US9443854B2Sep 13, 2016
FinFET with constrained source-drain epitaxial region
IBM1 citations63
US9673197B2Jun 6, 2017
FinFET with constrained source-drain epitaxial region
IBM0 citations52
US9536879B2Jan 3, 2017
FinFET with constrained source-drain epitaxial region
IBM0 citations52
US9299780B2Mar 29, 2016
Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
IBM0 citations52
US9252215B2Feb 2, 2016
Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
IBM0 citations52