Inventor

COLLINS DAVID S

US34 patents

⚠️ This page may combine multiple inventors who share the name “COLLINS DAVID S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COLLINS DAVID S

IBM

Asymmetric junction field effect transistor

Latchup robust gate array using through wafer via

ESD design, verification and checking system and method of use

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Design methodology of guard ring design resistance optimization for latchup prevention

Deep trench varactors

Structure and method for enhanced triple well latchup robustness

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Metal wiring structure for integration with through substrate vias

Lateral passive device having dual annular electrodes

Optimized device isolation

Structure for a latchup robust array I/O using through wafer via

Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise

Structure for a latchup robust gate array using through wafer via

Method for symmetric capacitor formation

Latchup robust array I/O using through wafer via

COLLINS DAVID S

Semiconductor structure having vias and high density capacitors

Lateral passive device having dual annular electrodes

Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors

Metal wiring structure for integration with through substrate vias

Metal fill structures for reducing parasitic capacitance

Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors

AMGEN INC

Composition and method for treating inflammatory diseases

Composition and method for treating inflammatory diseases

Composition and method for treating inflammatory diseases

BOTULA ALAN BERNARD

Method and structures for improving substrate loss and linearity in SOI substrates

SOI (silicon on insulator) substrate improvements

ANDERSON FREDERICK G

Asymmetric junction field effect transistor

CHAPMAN PHILLIP F

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry