Inventor

RASSEL ROBERT M

US102 patents

⚠️ This page may combine multiple inventors who share the name “RASSEL ROBERT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RASSEL ROBERT M

IBM

Semiconductor devices

Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit

FEOL/MEOL metal resistor for high end CMOS

Terminal pad structures and methods of fabricating same

Semiconductor structure

Tunable temperature coefficient of resistance resistors and method of fabricating same

Asymmetric junction field effect transistor

Structure and method of hyper-abrupt junction varactors

Heat sink for integrated circuit devices

Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate

Wrapped gate junction field effect transistor

Junction field effect transistor with a hyperabrupt junction

Deep trench based far subcollector reachthrough

Structure and method for fabrication JFET in CMOS

Tunable temperature coefficient of resistance resistors and method of fabricating same

Semiconductor structure including trench capacitor and trench resistor

Terminal pad structures and methods of fabricating same

Semiconductor structure and method of manufacture

Method of fabricating a precision buried resistor

MOS varactor using isolation well

MOS varactor with segmented gate doping

Precision polysilicon resistor process

Structure and method for hyper-abrupt junction varactors

Back-end-of-line metal-oxide-semiconductor varactors

Design structure with a deep sub-collector, a reach-through structure and trench isolation

Deep trench varactors

Schottky barrier diodes for millimeter wave SiGe BICMOS applications

Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit

Semiconductor devices

Semiconductor devices

COOLBAUGH DOUGLAS D

Method of making heat sink for integrated circuit devices

Silicided trench contact to buried conductive layer

MIM capacitor structure in FEOL and related method

Method of cooling a resistor

COLLINS DAVID S

Semiconductor structure having vias and high density capacitors

Lateral passive device having dual annular electrodes

Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors

GAMBINO JEFFREY P

Interlevel conductive light shield

Intralevel conductive light shield

Interlevel conductive light shield

ANDERSON FREDERICK G

Asymmetric junction field effect transistor

Schottky barrier diode with perimeter capacitance well junction

CHENG KANGGUO

Semiconductor structure including trench capacitor and trench resistor

GLOBALFOUNDRIES INC

Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias

ORNER BRADLEY A

Deep trench based far subcollector reachthrough

CAMPI JOHN B

Double gate depletion mode MOSFET

HERSHBERGER DOUGLAS B

Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET

BOTULA ALAN B

Forming structures on resistive substrates

LIU XUEFENG

Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology

RASSEL ROBERT M

Schottky barrier diode, a method of forming the diode and a design structure for the diode