Inventor

XUE YAN XUN

US98 patents

⚠️ This page may combine multiple inventors who share the name “XUE YAN XUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XUE YAN XUN

XUE YAN XUN

Wafer level package structure and the fabrication method thereof

Packaging method of molded wafer level chip scale package (WLCSP)

Process to form semiconductor packages with external leads

Power device with bottom source electrode

Packaging method of molded wafer level chip scale package (WLCSP)

Semiconductor package of a flipped MOSFET and its manufacturing method

Stacked power semiconductor device using dual lead frame and manufacturing method

Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors

Top exposed package and assembly method

Method of attaching an interconnection plate to a semiconductor die within a leadframe package

Packaged power semiconductor with interconnection of dies and metal clips on lead frame

Semiconductor device employing aluminum alloy lead-frame with anodized aluminum

Semiconductor encapsulation and method thereof

Method for packaging a power device with bottom source electrode

Method and structure for wafer level packaging with large contact area

Stacked power semiconductor device using dual lead frame

Wafer level chip scale package with thick bottom metal exposed and preparation method thereof

Packaging method with backside wafer dicing

Wafer level packaging structure with large contact area and preparation method thereof

Metal oxide semiconductor field effect transistor integrating a capacitor

Method of making a copper wire bond package

Method of integrating a MOSFET with a capacitor

ALPHA & OMEGA SEMICONDUCTOR

Semiconductor power device having single in-line lead module and method of making the same

Wafer level chip scale package with exposed thick bottom metal

Semiconductor device with thick bottom metal and preparation method thereof

Power semiconductor package device having locking mechanism, and preparation method thereof

Power device and preparation method thereof

Wafer level chip scale package

Chip-exposed semiconductor device

Method for preparing semiconductor devices applied in flip chip technology

Semiconductor package with small gate clip and assembly method

Semiconductor package with small gate clip and assembly method

GONG YUPING

Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET

Semiconductor wafer level package (WLP) and method of manufacture thereof

Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method

Chip-exposed semiconductor device and its packaging method

YILMAZ HAMZA

Stacked dual chip package and method of fabrication

Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures

Stacked multi-chip bottom source semiconductor device and preparation method thereof

HO YUEH-SE

Combined packaged power semiconductor device

Stacked dual-chip packaging structure and preparation method thereof

Combined packaged power semiconductor device

ALPHA & OMEGA SEMICONDUCTOR INT LP

Semiconductor package having a lead frame including die paddles and method of making the same

Chip scale semiconductor package having back side metal layer and raised front side pad and method of making the same

Wafer level chip scale semiconductor package

SHI LEI

Power semiconductor device package method

Flip-chip semiconductor chip packing method

ALPHA & OMEGA SEMICONDUCTOR CAYMAN LTD

Semiconductor package including low side field-effect transistors and high side field-effect transistors and method of making the same

Double-side exposed semiconductor device

LU JUN

Semiconductor packaging and fabrication method using connecting plate for internal connection