Inventor

SCOTT STEVEN L

US48 patents

⚠️ This page may combine multiple inventors who share the name “SCOTT STEVEN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCOTT STEVEN L

CRAY INC

Decoupled scalar/vector computer architecture system and method

Multistream processing memory-and barrier-synchronization method and apparatus

Collective engine method and apparatus

Speculative forwarding in a high-radix router

Remote translation mechanism for a multi-node system

Optimized high bandwidth cache coherence mechanism

Optimized high bandwidth cache coherence mechanism

System and method for processing memory instructions using a forced order queue

Latency tolerant distributed shared memory multiprocessor computer

Reduced arbitration routing system and method

Flexible routing tables for a high-radix router

Atomic memory operation cache protocol with opportunistic combining

Load balancing for communications within a multiprocessor computer system

Multiprocessor system having processors with different address widths and method for operating the same

Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system

CRAY RESEARCH INC

Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller

Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue&#39;s tail pointer structure in local memory

Stream buffers for high-performance computer memory system

Adaptive routing mechanism for torus interconnection network

Seralized race-free virtual barrier network

Using external registers to extend memory reference capabilities of a microprocessor

System for randomly modifying virtual channel allocation and accepting the random modification based on the cost function

Adaptive congestion control mechanism for modular computer networks

Adaptive congestion control mechanism for modular computer networks

Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers

SCOTT STEVEN L

Relaxed memory consistency model

Flexible routing tables for a high-radix router

High-radix interprocessor communications system and method

One-way message notification with out-of-order packet delivery

Software emulation of massive hardware threading for tolerating remote memory references

Global clock via embedded spanning tree

Routing table architecture

Reliable message transport network

SILICON GRAPHICS INC

System and method for fast barrier synchronization

Remote address translation in a multiprocessor system

Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure

System and method for fault-tolerant transmission of data within a dual ring network

Node translation and protection in a clustered multiprocessor system

INTEL CORP

Dragonfly processor interconnect network

Dragonfly processor interconnect network

Flexible routing tables for a high-radix router

Extended fast memory access in a multiprocessor computer system

ABTS DENNIS C

Error management watchdog timers in a multiprocessor computer

Extended fast memory access in a multiprocessor computer system

Error management firewall in a multiprocessor computer

HEWLETT PACKARD ENTPR DEV LP

Switch device for facilitating switching in data-driven intelligent network

Switch device for facilitating switching in data-driven intelligent network

FAANES GREGORY J

Configurable vector length computer processor

Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory