Inventor

HAMMARLUND PER

US73 patents

⚠️ This page may combine multiple inventors who share the name “HAMMARLUND PER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMMARLUND PER

INTEL CORP

Primitives to enhance thread-level speculation

Stick and spoke replay with selectable delays

Queued locks using monitor-memory wait

Queued locks using monitor-memory wait

Stopping replay tornadoes

Access control of a resource shared between components

Speculative multi-threading for instruction prefetch and/or trace pre-build

Safe store for speculative helper threads

Method and apparatus for speculative execution of uncontended lock instructions

Methods and apparatus for generating speculative helper thread spawn-target points

Programmable event driven yield mechanism which may activate other threads

Method and apparatus for efficient utilization for prescient instruction prefetch

System and method for storing immediate data

Mechanism to exploit synchronization overhead to improve multithreaded performance

Queued locks using monitor-memory wait

Predicting contention in a processor

Method and apparatus for cost and power efficient, scalable operating system independent services

Programmable event driven yield mechanism which may activate service threads

Synchronizing recency information in an inclusive cache hierarchy

Sequencer address management

Resolving false dependencies of speculative load instructions

Providing a backing store in user-level memory

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Method and apparatus for efficient resource utilization for prescient instruction prefetch

Flow optimization and prediction for VSSE memory operations

System and method for storing immediate data

System and method for storing immediate data

Programmable event driven yield mechanism which may activate other threads

Programmable event driven yield mechanism which may activate other threads

Technique for thread communication and synchronization

Programmable event driven yield mechanism which may activate other threads

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode

Instruction for enabling a processor wait state

Operation frame filtering, building, and execution

System and method for storing immediate data

Operation frame filtering, building, and execution

Technique for using memory attributes

WANG HONG

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Speculative multi-threading for instruction prefetch and/or trace pre-build

Programmable event driven yield mechanism which may activate other threads

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

User-level privilege management

Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

DIXON MARTIN G

Instruction for enabling a processor wait state

ZOU XIANG

Programmable event-driven yield mechanism

KUMAR ARVIND

Method and apparatus for cost and power efficient, scalable operating system independent services

JOURDAN STEPHAN

Vector completion mask handling

SCHUCHMAN ETHAN

Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode

HAMMARLUND PER

Inter-processor interrupts