Inventor
HINTON GLENN
US30 patents
⚠️ This page may combine multiple inventors who share the name “HINTON GLENN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS5680565AOct 21, 1997
Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions
INTEL CORP53 citations95
US4811208AMar 7, 1989
Stack frame cache on a microprocessor chip
INTEL CORP101 citations93
US9786338B2Oct 10, 2017
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP9 citations92
US7856633B1Dec 21, 2010
LRU cache replacement for a partitioned set associative cache
INTEL CORP49 citations92
US7111153B2Sep 19, 2006
Early data return indication mechanism
INTEL CORP20 citations90
US10170165B2Jan 1, 2019
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP4 citations84
US10163468B2Dec 25, 2018
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP5 citations84
US10153011B2Dec 11, 2018
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP4 citations84
US10153012B2Dec 11, 2018
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP3 citations84
US10141033B2Nov 27, 2018
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP4 citations84
US10102888B2Oct 16, 2018
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP4 citations84
US9424034B2Aug 23, 2016
Multiple register memory access instructions, processors, methods, and systems
INTEL CORP8 citations84
US8386823B2Feb 26, 2013
Method and apparatus for cost and power efficient, scalable operating system independent services
INTEL CORP7 citations83
US7757045B2Jul 13, 2010
Synchronizing recency information in an inclusive cache hierarchy
INTEL CORP14 citations83
US7404065B2Jul 22, 2008
Flow optimization and prediction for VSSE memory operations
INTEL CORP7 citations73
US10469557B2Nov 5, 2019
QoS based binary translation and application streaming
INTEL CORP2 citations70
US7567471B2Jul 28, 2009
High speed fanned out system architecture and input/output circuits for non-volatile memory
INTEL CORP2 citations63
US8631259B2Jan 14, 2014
Method and apparatus for quick resumption of a processing system with volatile memory
INTEL CORP1 citations61
US7451295B2Nov 11, 2008
Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
INTEL CORP2 citations60
US9525586B2Dec 20, 2016
QoS based binary translation and application streaming
INTEL CORP2 citations54
US7457938B2Nov 25, 2008
Staggered execution stack for vector processing
INTEL CORP1 citations52
US7457932B2Nov 25, 2008
Load mechanism
INTEL CORP0 citations52
US7062640B2Jun 13, 2006
Instruction segment filtering scheme
INTEL CORP1 citations52