Inventor

SINHA JAYDEEP

US30 patents

⚠️ This page may combine multiple inventors who share the name “SINHA JAYDEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINHA JAYDEEP

KLA TENCOR CORP

Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Detection of selected defects in relatively noisy inspection data

Process-induced distortion prediction and feedforward and feedback correction of overlay errors

System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking

Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements

System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking

Prediction based chucking and lithography control optimization

Systems and methods for wafer structure uniformity monitoring using interferometry wafer geometry tool

Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool

Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool

Systems and methods for wafer surface feature detection and quantification

Predictive wafer modeling based focus error prediction using correlations of wafers

Hybrid phase unwrapping systems and methods for patterned wafer measurement

Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool

Systems and methods of advanced site-based nanotopography for wafer surface metrology

Using wafer geometry to improve scanner correction effectiveness for overlay control

Patterned wafer geometry measurements for semiconductor process controls

Detection of selected defects in relatively noisy inspection data

Prediction based chucking and lithography control optimization

Using wafer geometry to improve scanner correction effectiveness for overlay control

Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance

Bright-field differential interference contrast system with scanning beams of round and elliptical cross-sections

Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry

ADE CORP

Ring chuck to hold 200 and 300 mm wafer

Wafer shape accuracy using symmetric and asymmetric instrument error signatures

Specimen topography reconstruction

Ring chuck to hold 200 and 300 mm wafer

CHEN HAIGUANG

Methods and systems for improved localized feature quantification in surface metrology tools

Systems and methods for wafer edge feature detection and quantification

VEERARAGHAVAN SATHISH

Site based quantification of substrate topography and its relation to lithography defocus and overlay