Inventor

BICKFORD JEANNE P

US68 patents

⚠️ This page may combine multiple inventors who share the name “BICKFORD JEANNE P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BICKFORD JEANNE P

IBM

Systems and methods for single cell product path delay analysis

System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time

Semiconductor device reliability model and methodologies for use thereof

Frequency selection with selective voltage binning

Testing method using a scalable parametric measurement macro

Method and system allowing for semiconductor design rule optimization

Method of facilitating integrated circuit design using manufactured property values

Method for modeling integrated circuit yield

Integrated circuit chip reliability qualification using a sample-specific expected fail rate

Multiple manufacturing line qualification

Reliability-optimized selective voltage binning

Balancing sensitivities with respect to timing closure for integrated circuits

Semiconductor device reliability model and methodologies for use thereof

Selective voltage binning within a three-dimensional integrated chip stack

Selective voltage binning leakage screen

Method and system for timing violations in a circuit

Power/performance optimization through continuously variable temperature-based voltage control

Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool

Computer readable medium, system and associated method for designing integrated circuits with loop insertions

Across reticle variation modeling and related reticle

Integrated circuit chip reliability qualification using a sample-specific expected fail rate

System integrator and system integration method with reliability optimized integrated circuit chip selection

BICKFORD JEANNE P

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Test path selection and test program generation for performance testing integrated circuit chips

System yield optimization using the results of integrated circuit chip performance path testing

Reliability evaluation and system fail warning methods using on chip parametric monitors

Systems and methods for system power estimation

Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes

Adaptive power control using timing canonicals

Integrated circuit product yield optimization using the results of performance path testing

Method and structure for multi-core chip product test and selective voltage binning disposition

Method and system to predict a number of electromigration critical elements

Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression

Disposition of integrated circuits using performance sort ring oscillator and performance path testing

Power/performance optimization through temperature/voltage control

Reliability evaluation and system fail warning methods using on chip parametric monitors

Circuit design with growable capacitor arrays

GLOBALFOUNDRIES INC

Temperature-aware integrated circuit design methods and systems

Integrated circuit chip reliability using reliability-optimized failure mechanism targeting

Integrated circuit chip design methods and systems using process window-aware timing analysis

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning

Electromigration-aware integrated circuit design methods and systems

System and method for identifying operating temperatures and modifying of integrated circuits

Systems and methods to prevent incorporation of a used integrated circuit chip into a product

ANDERSON BRENT A

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

ANEMIKOS THEODOROS E

Speed binning for dynamic and adaptive power control

MENTOR GRAPHICS CORP

Reliability evaluation and system fail warning methods using on chip parametric monitors