Inventor
KUEMERLE MARK W
US22 patents
⚠️ This page may combine multiple inventors who share the name “KUEMERLE MARK W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
8 patentsUS9619609B1Apr 11, 2017
Integrated circuit chip design methods and systems using process window-aware timing analysis
GLOBALFOUNDRIES INC6 citations73
US9552447B2Jan 24, 2017
Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling
GLOBALFOUNDRIES INC4 citations73
US10714411B2Jul 14, 2020
Interconnected integrated circuit (IC) chip structure and packaging and method of forming same
GLOBALFOUNDRIES INC2 citations71
US9875956B1Jan 23, 2018
Integrated interface structure
GLOBALFOUNDRIES INC2 citations70
US9870163B2Jan 16, 2018
Double bandwidth algorithmic memory array
GLOBALFOUNDRIES INC1 citations52
US9372520B2Jun 21, 2016
Reverse performance binning
GLOBALFOUNDRIES INC0 citations52
US10381304B2Aug 13, 2019
Interconnect structure
GLOBALFOUNDRIES INC0 citations51
US9865486B2Jan 9, 2018
Timing/power risk optimized selective voltage binning using non-linear voltage slope
GLOBALFOUNDRIES INC1 citations51
IBM
7 patentsUS7475366B2Jan 6, 2009
Integrated circuit design closure method for selective voltage binning
IBM53 citations94
US9269407B1Feb 23, 2016
System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time
IBM14 citations84
US9501607B1Nov 22, 2016
Composite views for IP blocks in ASIC designs
IBM4 citations73
US8839165B2Sep 16, 2014
Power/performance optimization through continuously variable temperature-based voltage control
IBM3 citations63
US9171125B2Oct 27, 2015
Limiting skew between different device types to meet performance requirements of an integrated circuit
IBM1 citations52
US8963620B2Feb 24, 2015
Controlling circuit voltage and frequency based upon location-dependent temperature
IBM1 citations52
US8843874B2Sep 23, 2014
Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures
IBM0 citations52