Inventor

LICHTENSTEIGER SUSAN K

US32 patents

⚠️ This page may combine multiple inventors who share the name “LICHTENSTEIGER SUSAN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LICHTENSTEIGER SUSAN K

IBM

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

Integrated circuit design closure method for selective voltage binning

System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time

Voltage island performance/leakage screen monitor for IP characterization

Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens

Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point

System and method to optimize semiconductor power by integration of physical design timing and product performance measurements

Method for static timing verification of integrated circuits having voltage islands

Method and system of modeling leakage

Power switch circuit sizing technique

Selective voltage binning leakage screen

Power/performance optimization through continuously variable temperature-based voltage control

Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block

Controlling circuit voltage and frequency based upon location-dependent temperature

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Product performance test binning

Method and apparatus for band printing with automatic home compensation

GLOBALFOUNDRIES INC

Integrated circuit chip design methods and systems using process window-aware timing analysis

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

Timing/power risk optimized selective voltage binning using non-linear voltage slope

Pre-test power-optimized bin reassignment following selective voltage binning

Pre-test power-optimized bin reassignment following selective voltage binning

BICKFORD JEANNE P

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Systems and methods for system power estimation

Power/performance optimization through temperature/voltage control

LICHTENSTEIGER SUSAN K

Structure for dynamically adjusting pipelined data paths for improved power management

Dynamically adjusting pipelined data paths for improved power management

Method of designing multi-state restore circuitry for restoring state to a power managed functional block

BUCK NATHAN C

Timing closure on multiple selective corners in a single statistical timing run

ANEMIKOS THEODOROS E

Speed binning for dynamic and adaptive power control

BUCK NATHAN

Chip design and fabrication method optimized for profit

ANEMIKOS THEODOROS

Product performance test binning