Inventor

KO CHUNG-CHI

TW119 patents

⚠️ This page may combine multiple inventors who share the name “KO CHUNG-CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KO CHUNG-CHI

TAIWAN SEMICONDUCTOR MFG CO LTD

Via patterning using multiple photo multiple etch

Low-K dielectric interconnect systems

Interconnect structure and method

Multi-patterning to form vias with straight profiles

Manufacturing method of semiconductor device

Via patterning using multiple photo multiple etch

Silicon oxide layer for oxidation resistance and method forming same

Fin field-effect transistor device and method of forming the same

Semiconductor device and method

Forming nitrogen-containing low-k gate spacer

Low-k feature formation processes and structures formed thereby

Forming nitrogen-containing low-K gate spacer

Low-k feature formation processes and structures formed thereby

Interconnect structure and method

Methods for reducing dual damascene distortion

Interconnect structure for semiconductor devices

Low-k feature formation processes and structures formed thereby

Damascene process using cap layer

Reducing oxidation by etching sacrificial and protection layer separately

Fin field-effect transistor device with composite liner for the Fin

Method of filling gaps with carbon and nitrogen doped film

Forming nitrogen-containing layers as oxidation blocking layers

Forming nitrogen-containing low-K gate spacer

Method of filling gaps with carbon and nitrogen doped film

Multi-patterning to form vias with straight profiles

Methods of forming FinFET device

Interconnect structure and method

Spacer structure with high plasma resistance for semiconductor devices

Via patterning using multiple photo multiple etch

Via patterning using multiple photo multiple etch

Interconnect structure with kinked profile

Low-k dielectric interconnect systems

Self-aligned repairing process for barrier layer

Selective repairing process for barrier layer

TAIWAN SEMICONDUCTOR MFG

Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer

Method for forming a carbon doped oxide low-k insulating layer

SiOCH low k surface protection layer formation by CxHy gas plasma treatment

Barrier layer for copper interconnect

Semiconductor device and fabrication method thereof

Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties

Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant

Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections

Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio

Method of preventing photoresist poisoning of a low-dielectric-constant insulator

ATR-FTIR metal surface cleanliness monitoring

Method for forming low dielectric constant damascene structure while employing a carbon doped silicon oxide capping layer

System for detecting surface defects in semiconductor wafers

KO CHUNG-CHI

Double patterning strategy for contact hole and trench in photolithography

SHIH PO-CHENG

Double patterning strategy for contact hole and trench in photolithography

CHANG HUI-LIN

Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties