Inventor

JAIN NAVNEET

US32 patents

⚠️ This page may combine multiple inventors who share the name “JAIN NAVNEET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAIN NAVNEET

GLOBALFOUNDRIES INC

Special constructs for continuous non-uniform active region FinFET standard cells

Structure and method for flexible power staple insertion

Special construct for continuous non-uniform active region FinFET standard cells

Special construct for continuous non-uniform active region FinFET standard cells

Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library

Special construct for continuous non-uniform RX FinFET standard cells

On-chip voltage generator for back-biasing field effect transistors in a circuit block

Contacting SOI subsrates

Structure and method for flexible power staple insertion

Calibration devices for I/O driver circuits having switches biased differently for different temperatures

Measuring setup and hold times using a virtual delay

Antenna diode circuit for manufacturing of semiconductor devices

Parameterized cell for planar and finFET technology design

GLOBALFOUNDRIES US INC

Semiconductor structure including sectioned well region

Semiconductor structure including sectioned well region

Transistor arrays with controllable gate voltage

Non-volatile static random access memory bit cells with ferroelectric field-effect transistors

Integrated circuit structure with cells having asymmetric power rail

Device structures for a high-voltage semiconductor device

System and method employing power-optimized timing closure

Memory device structures that include a capacitor

MASTERCARD INTERNATIONAL INC

Methods and systems for facilitating payment transactions at point of sale terminals

Electronic system and method for transaction processing

System and method for electronic payment on delivery

Electronic payment processing apparatus and method

System for executing a computer process for processing a transaction, and related computer process

Method and system for facilitating sharing of reward points

RASHED MAHBUB

Methods of using a trench salicide routing layer

Providing timing-closed FinFET designs from planar designs

GLOBALFOUNDRIES DRESDEN MOD 1

Well contact cell with doped tap region separated from active region, and methods to form same

GLOBALFOUNDARIES INC

Integrating optimal planar and three-dimensional semiconductor design layouts

MASTERCARD INT INCORPORTED

Electronic system and method for transaction processing