Inventor

RASHED MAHBUB

US73 patents

⚠️ This page may combine multiple inventors who share the name “RASHED MAHBUB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RASHED MAHBUB

GLOBALFOUNDRIES INC

Special constructs for continuous non-uniform active region FinFET standard cells

Methods for improving double patterning route efficiency

Structure and method for flexible power staple insertion

Special construct for continuous non-uniform active region FinFET standard cells

Special construct for continuous non-uniform active region FinFET standard cells

Cross-coupling-based design using diffusion contact structures

Wide pin for improved circuit routing

Densely packed standard cells for integrated circuit products, and methods of making same

Standard cell connection for circuit routing

Power rail layout for dense standard cell library

Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library

Method, apparatus and system for forming recolorable standard cells with triple patterned metal layer structures

Special construct for continuous non-uniform RX FinFET standard cells

Wide pin for improved circuit routing

Memory bit cell for reduced layout area

Method and apparatus for assisted metal routing

Method and apparatus for modified cell architecture and the resulting device

Forming modified cell architecture for finFET technology and resulting device

Semiconductor device with transistor local interconnects

FDSOI semiconductor device with contact enhancement layer and method of manufacturing

Electrostatic discharge protection device

On-chip voltage generator for back-biasing field effect transistors in a circuit block

Circuit design having aligned power staples

Memory bit cell for reduced layout area

Bit cell with double patterned metal layer structures

Variable power rail design

Structure and method for flexible power staple insertion

Calibration devices for I/O driver circuits having switches biased differently for different temperatures

GLOBALFOUNDRIES US INC

Semiconductor structure including sectioned well region

Semiconductor device with transistor local interconnects

Single-rail memory circuit with row-specific voltage supply lines and boost circuits

Semiconductor structure including sectioned well region

Semiconductor device with transistor local interconnects

Low clock load dynamic dual output latch circuit

Integrated circuit structure with cells having asymmetric power rail

Antenna structure

Local interconnect power rails and upper power rails

RASHED MAHBUB

Cross-coupling based design using diffusion contact structures

Semiconductor device with transistor local interconnects

Semiconductor device with transistor local interconnects

Methods of using a trench salicide routing layer

Middle-of-the-line constructs using diffusion contact structures

Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same

YUAN LEI

Double patterning compatible colorless M1 route

Integrated circuits and methods for fabricating integrated circuits using double patterning processes

MA YUANSHENG

Layout designs with via routing structures

WANG YAN

Cross-coupling-based design using diffusion contact structures

DOMAN DAVID S

Software and method for via spacing in a semiconductor device

GLOBALFOUNDARIES INC

Integrating optimal planar and three-dimensional semiconductor design layouts

KIM JUHAN

Bit cell with double patterned metal layer structures