Inventor

BERZINS MATTHEW

US22 patents

⚠️ This page may combine multiple inventors who share the name “BERZINS MATTHEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERZINS MATTHEW

SAMSUNG ELECTRONICS CO LTD

Low power toggle latch-based flip-flop including integrated clock gating logic

Multi-bit flip-flops and scan chain circuits

System and method for improving scan hold-time violation and low voltage operation in sequential circuit

Low power integrated clock gating cell using controlled inverted clock

Power rail for standard cell block

Low power integrated clock gating system and method

Low-power low-setup integrated clock gating cell with complex enable selection

Power grid and standard cell co-design structure and methods thereof

Method for reducing power consumption in scannable flip-flops without additional circuitry

Multi-bit flip-flops

System and method for improving scan hold-time violation and low voltage operation in sequential circuit

Dynamic flip flop having data independent P-stack feedback

Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell

Semiconductor circuit including flip-flop

BERZINS MATTHEW

Apparatus for low power high speed integrated clock gating cell

Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

High speed domino-based flip flop

KIM MIN-SU

Multi-bit flip-flops and scan chain circuits

CYPRESS SEMICONDUCTOR CORP

Circuit and method for rapid power up of a differential output driver

MILLAR BRIAN

Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design

WELLS CHRISTINA

Flip-flop with zero-delay bypass mux

Lim James Jung

Low power integrated clock gating cell with internal control signal