Inventor
MOHARIR SUDHIR S
IN14 patents
⚠️ This page may combine multiple inventors who share the name “MOHARIR SUDHIR S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SKAN TECH CORP
7 patentsUS9490008B1Nov 8, 2016
9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
SKAN TECH CORP20 citations90
US9697888B1Jul 4, 2017
9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
SKAN TECH CORP8 citations82
US9786358B1Oct 10, 2017
6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write
SKAN TECH CORP2 citations71
US9627043B1Apr 18, 2017
9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
SKAN TECH CORP2 citations71
US9496029B1Nov 15, 2016
6T bitcell for dual port SRAM memories with single-ended read and single-ended write and optimized bitcells for multiport memories
SKAN TECH CORP3 citations71
US9653150B1May 16, 2017
Static random access memory (SRAM) bitcell and memory architecture without a write bitline
SKAN TECH CORP0 citations50
US9672904B1Jun 6, 2017
6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write
SKAN TECH CORP0 citations39
SKAN TECH CORPORATION
3 patentsUS10026493B1Jul 17, 2018
PPA (power performance area) efficient architecture for rom (read only memory) and a ROM bitcell without a transistor
SKAN TECH CORPORATION0 citations48
US10014065B1Jul 3, 2018
PPA (power performance area) efficient architecture for ROM (read only memory) and a ROM bitcell without a transistor
SKAN TECH CORPORATION0 citations48
US10008280B1Jun 26, 2018
PPA (power performance area) efficient architecture for ROM (read only memory) and a ROM bitcell without a transistor
SKAN TECH CORPORATION0 citations48